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You’ve got the power: controlling power consumption in the Zynq UltraScale+ MPSoC

Xilinx Employee
Xilinx Employee
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The Xilinx Zynq UltraScale+ MPSoC contains a lot of goodies for system designers including four or six ARM processor cores (two or four 64-bit ARM Cortex-A53 application processor cores and two 32-bit Arm Cortex-R5 real-time processor cores) and plenty of advanced UltraScale+ programmable logic. One of the many unsung goodies under the Zynq UltraScale+ MPSoC’s hood is extensive power control—and lots of it.


There are three major power domains inside of the device’s processing system and one for the programmable logic, as shown below:



Zynq MPSoC Power Domains.jpg 

Zynq UltraScale+ MPSoC Power Domains



Each of the Zynq UltraScale+ MPSoC power domains draws power from separate power pins that you can connect to different external power regulators for independent power control. (Note: If your design does not require individual power-domain control, these power rails can share power supplies.)


The Zynq UltraScale+ MPSoC processing system’s three power domains include:


  • The battery-power domain
  • The low-power domain
  • The full-power domain


The battery-power domain contains battery-backed RAM, used for storing an encryption key, and a real-time clock with external crystal oscillator to sustain timekeeping even when the rest of the device is powered off. This domain is designed to be powered by an external battery. Power consumption for the battery-power mode ranges from 180nW when just powering the battery-backed RAM to 3μW when the real-time clock is enabled.


The low-power domain consists of a real-time processor unit with the two ARM Cortex-R5 processors, static on-chip memory, the platform management unit, the configuration and security unit, and low-speed peripherals. Power consumption for the low-power mode associated with the low-power domain ranges from about 20mW to about 400mW.


The full-power domain consists of the application processor unit, based on four ARM Cortex-A53 processors, the GPU, the DDR memory controller, and high-performance peripherals including PCIe, USB 3.0, DisplayPort, and SATA. Power consumption for the full-power mode depends on processor activity and how many processor cores are enabled. Power consumption in this mode can range up to a couple of watts.


The programmable-logic power domain includes logic cells, block RAMs, DSP blocks, the XADC, I/O ports, and high-speed serial interfaces. Other devices in the programmable-logic power domain include the video codec, PCIe Gen4 controller, UltraRAM, the 100G Ethernet MAC, and Interlaken I/O. Power consumption for the programmable logic depends entirely on what and how much you put into the programmable logic and how fast you clock it.


Each power domain in the Zynq UltraScale+ MPSoC’s processing system contains multiple independent power islands that you can gate individually for fine-grained power management. The power islands within the low-power domain include:


  • The two ARM Cortex-R5 processors (power-gated as a pair)
  • Two tightly-coupled memories connected to the Cortex-R5s (each with four individually power-gated banks)
  • On-Chip Memory (with four individually power-gated banks)
  • Two USB ports (each individually power-gated)


The power islands within the full-power domain include:


  • The four ARM Cortex-A53 application processors (each can be individually power-gated)
  • L2 cache servicing the Cortex-A53 processors
  • The two pixel processors in GPU (each can be individually power-gated)


You’ll probably want a lot more information about the Zynq UltraScale+ MPSoC’s power-management features, so I recommend downloading a copy of the new Whitepaper titled “Managing Power and Performance with the Zynq UltraScale+ MPSoC” by Glenn Steiner and Brian Philofsky.









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