There is no PCIe Gen5—yet—but there’s a 32Gbps/lane future out there and TE Connectivity demonstrated that future at this week’s DesignCon 2018. The demo’s real purpose was to show the capabilities of TE Connectivity’s Sliver connector system which includes card-edge and cabled connectors. In the demo at DesignCon, four channels carry 32Gbps data streams through surface-mount and right-angle connectors to create a mockup of a future removable-storage device. Those 32Gbps data streams are generated, transmitted, and received by bulletproof Xilinx UltraScale+ GTY transceivers operating reliably at a theoretical PCIe Gen5’s 32Gbps/lane data rate despite 35dB of loss through the demo system.
In the following short video, Samtec’s Ralph Page describes the demo and mentions the nice eyes and clear data levels, as seen on the Xilinx demo software screen positioned above the demo boards. He also mentions the BER—5.29x10-8. That’s the error rate before adding the error-reducing capabilities of a FEC, which can drop the error rate by perhaps another ten orders of magnitude or more.
Samtec’s demo points to a foreseeable future where you will be able to develop large backplanes with screamingly fast performance using PAM4 SerDes transceivers.
The 2-minute video below shows you an operational Xilinx Virtex UltraScale+ XCVU37P FPGA, which is enhanced with co-packaged HBM (high-bandwidth memory) DRAM using Xilinx’s well-proven, 3rd-generation 3D manufacturing process. (Xilinx started shipping 3D FPGAs way back in 2011, starting with the Virtex-7 2000T and we’ve been shipping these types of devices ever since.)
This video was made on the very first day of silicon bringup for the device and it is already operating at full speed (460Gbytes/sec), error-free, over 32 channels. The Virtex UltraScale+ XCVU37P is one big All Programmable device with:
2852K System Logic Cells
9Mbits of BRAM
270Mbits of UltraRAM
9024 DSP48E2 slices
8Gbytes of integrated HBM DRAM
96 32.75Gbps GTY SerDes transceivers
Whatever your requirements, whatever your application, chances are this extremely powerful FPGA will deliver all of the heavy lifting (processing, memory, and I/O) that you need.
Curtiss-Wright’s VPX3-535 3U OpenVPX transceiver module implements a single-slot, dual-channel, 6Gsamples/sec analog data-acquisition and processing system using two 12-bit, 6Gsamples/sec ADCs and two 12-bit, 6Gsamples/sec DACs. This is the type of capability you need for demanding applications such as radar, Signal Intelligence (SIGINT), Electronic Warfare (EW), and Software Defined Radio (SDR). This amount of analog-to-digital and digital-to-analog conversion capability demands wicked-fast digital processing and on the VPX3-535 transceiver module, that digital processing comes in the form of two of Xilinx’s most powerful All Programmable devices: a Virtex UltraScale+ VU9P and a Zynq UltraScale+ ZU4 MPSoC.
Here’s a block diagram of the Curtiss-Wright VPX3-535 module:
The VPX3-535 is Curtiss-Wright’s first publicly announced module to feature full compliance to the VITA 48.8 Air-Flow-Through (AFT) cooling standard, which ensures optimal performance in the harshest conditions. VITA 48.8 provides a low-cost, effective means to cool high-power COTS 3U and 6U VPX modules that dissipate ~150W+.
At the same time, Curtiss-Wright is also introducing a conduction-cooled variant, called the VPX3-534, which designed for applications that do not require the performance of the VPX3-535. The VPX3-534 supports the same dual-channel, 12-bit, 6Gsamples/sec ADC and DAC channels as the VPX3-535 but it replaces the Virtex UltraScale+ FPGA with a Xilinx Kintex UltraScale KU115 FPGA. This module also supports an option for four 3Gsamples/sec ADC channels.
Please contact Curtiss-Wright directly for more information about the VPX3-535 and VPX3-534 OpenVPX transceiver modules.
Keysight published a 14-minute video back in 2015 that gives you the basics behind RF beamforming and its use in 5G applications. The video also invites you to download a free, 30-day trial of Keysight’s SystemVue with Keysight’s 5G simulation library to try out some of the concepts discussed in the video and the link appears to be active still.
Here’s the video:
Meanwhile, should you need an implementation technology for RF beamforming (5G or otherwise), allow me to suggest that the new Xilinx Zynq UltraScale+ RFSoC with its many integrated RF ADCs and DACs be at the top of your technology choices. There is literally no other device like the Zynq UltraScale+ RFSoC. It’s in a category of one.
For more information about the Zynq UltraScale+ RFSoC, see:
5G NR gNodeB deployments start as early as mid CY2019. Three key challenges:
Instantiating gNodeB and NGCore network functions in Telco Cloud
Next-generation fronthaul that enables gNodeB functional partitioning
Massive MIMO radios
A Xilinx session at Mobile World Congress (MWC) on March 1 titled “Enabling 5G NR Deployments” will discuss these three facets of 5G NR and strategies needed to overcome these challenges in three separate presentations. The presentation titles are:
5G NR acceleration in Telco Cloud
5G Transport Network and Packet Based Fronthaul
Implementing 5G NR Massive MIMO Radio
The three presenters are:
Awanish Verma, Senior Architect and Product Manager in Xilinx’s Communication Business Unit
Harpinder Matharu, Director of the Communications Business at Xilinx
Raghu Rao, Principal Architect and Director of Strategic Marketing for Wireless Products at Xilinx
The three presenters will also discuss real-world lessons learned while working with the supply chain—including operators, system vendors, semiconductor and software providers—in building 5G proofs of concepts and trial testbeds.
The hour-long event starts at 1:00pm and is being held in Hall 8.0, NEXTech Theatre F at MWC in Barcelona.
The recent introduction of the groundbreaking Xilinx Zynq UltraScale+ RFSoC means that there are big changes in store for the way advanced RF and comms systems will be designed. With as many as 16 RF-class ADCs and DACs on one device along with a metric ton or two of other programmable resources, the Zynq UltraScale+ RFSoC makes it possible to start thinking about single-chip Massive MIMO systems. A new EDN.com article by Paul Newson , Hemang Parekh, and Harpinder Matharu titled “Realizing 5G New Radio massive MIMO systems” teases a few details for building such systems and includes this mind-tickling photo:
A sharp eye and keen memory will link that photo to a demo from last October’s Xilinx Showcase demo at the Xilinx facility in Longmont, Colorado. Here’s Xilinx’s Lee Hansen demonstrating a similar system based on the Xilinx Zynq UltraScale+ RFSoC:
For more details about the Zynq UltraScale+ RFSoC, contact your friendly neighborhood Xilinx or Avnet sales rep and see these previous Xcell Daily blog posts:
Fairwave’s XTRX, a “truly” embedded SDR (software-defined radio) module now up as a Crowd Supply crowdfunding project, manages to pack an entire 2x2 MIMO SDR with an RF tuning range of 30MHz to 3.8GHz into a diminutive Mini PCIe format (30x51mm) by pairing Lime Microsystems’ LMS7002M 2nd-generation field-programmable RF Transceiver with a Xilinx Artix-7 35T FPGA. As of today, the project is 84% funded with 27 days left in the funding period and 317 pledges. The industry-standard Mini PCIe form factor allws you to embed the XTRX SDR module just about anywhere. According to Fairwaves, the XTRX is compatible with all of the popular SDR development tool suites.
Fairwaves’ XTRX 2x2 MIMO SDR Mini PCIe Module
Here’s a block diagram of the XTRX SDR module:
Fairwaves’ XTRX 2x2 MIMO SDR Module Block Diagram
Perhaps even more interesting, here’s a comparison chart that Fairwaves developed to point out the advantages of the XTRX SDR module:
Need something more complex than a 2x2 MIMO arrangement? There’s a PCIe Octopack carrier board that accepts as many as eight XTRX Mini PCIe modules (four on each side) creating a 16x16 MIMO SDR and you can synchronize multiple Octopack boards to create massive-MIMO configurations.
The Raptor from Rincon Research implements a 2x2 MIMO SDR (software-defined radio) in a compact 5x2.675-inch form factor by combining the capabilities of the Analog Devices AD9361 RF Agile Transceiver and the Zynq UltraScale+ ZU9EG MPSoC. The board has an RF tuning range of 70MHz to 6GHz. On-board memory includes 4Gbytes of DDR4 SDRAM, a pair of QSPI Flash memory chips, and an SD card socket. Digital I/O options include three on-board USB connectors (two USB 3.0 ports and one USB 2.0 port) and, through a mezzanine board, 10/100/1000 Ethernet, two SFP+ optical cages, an M.2 SATA port, DisplayPort, and a Samtec FireFly connector. Rincon Research provides the board along with a BSP, drivers, and COTS tool support.
Here’s a block diagram of the Raptor board:
Rincon Research’s Raptor, a 2x2 MIMO SDR Board, Block Diagram
Here are photos of the Raptor main board and its I/O expansion mezzanine board:
Rincon Research’s Raptor 2x2 MIMO SDR Board
Rincon Research’s Raptor I/O Expansion Board
Please contact Rincon Research for more information about the Raptor SDR.
Members of the Xilinx Zynq UltraScale+ RFSoC device family integrates multi-gigasample/sec RF ADCs and DACs, soft-decision forward error correction (SD-FEC) IP blocks, Xilinx UltraScale architecture programmable logic fabric, and an Arm Cortex-A53/Cortex-R5 multi-core processing subsystem into one chip. The Zynq UltraScale+ RFSoC is a category killer for many, many applications that need “high-speed analog-in, high-speed analog-out, digital-processing-in-the-middle” capabilities due to the devices’ extremely high integration level. It most assuredly will reduce the size, power, and complexity of traditional antenna structures in many RF applications—especially for 5G antenna systems.
As I wrote when the Zynq UltraScale+ RFSoC family won the IET Innovation Award in the Communications category, “There's simply no other device like the Zynq UltraScale+ RFSoC on the market, as suggested by this award. “
Zynq UltraScale+ RFSoC Conceptual Diagram
For more information about the Zynq UltraScale+ RFSoC, see:
Designing SDRs (software-defined radios)? MathWorks and Analog Devices have joined together to bring you a free Webinar titled “Radio Deployment on SoC Platforms.” It a 45-minute class that discusses hardware and software development for SDR designs using MathWorks’ MATLAB, Simulink, and HDL Coder to:
Model and simulate radio designs
Verify algorithms in simulation with streaming RF data
Deploy radio designs on hardware with HDL and C-code generation
Analog Devices’ Zynq-based RF SOM on a Carrier Card
There will be three broadcasts of the Webinar on December 13 to accommodate viewers around the world. Register here. Register even if you cannot attend and you’ll receive a link to a recording of the session.
Thirty years ago, my friends and co-workers Jim Reyer and KB and I would drive to downtown Denver for a long lunch at a dive Mexican bar officially known as “The Brewery Bar II.” But the guy who owned it, the guy who was always perched on a stool inside to the door to meet and seat customers, was named Abe Schur so we called these trips “Abe’s runs.” This week, I found myself in downtown Denver again at the SC17 supercomputer conference at the Colorado Convention Center. The Brewery Bar II is still in business and only 15 blocks away from the convention center, so on a fine, sunny day, I set out on foot for one more Abe’s run.
I arrived about 45-minutes later.
I walked in the front door and 30 years instantly evaporated. I couldn’t believe it but the place didn’t look any different. The same rickety tables. The same neon signs on the wall. The same bar. The same weird red, flocked wallpaper. It was all the same except my friends weren’t there with me and Abe wasn’t sitting on a stool. I’d already known that he’d passed away many years ago.
Also the same was the crowded state of the place at lunch time. The waitress (they don’t have servers at Abe’s) told me there were no tables available but I could eat at the bar. I took a place at the end of the bar and sat next to a guy typing on a laptop. That wasn’t the same as it was 30 years ago.
The bartender came up and asked me what I wanted to drink. I said I’d not been in for more than 25 years and asked if they still served “Tinys.” A Tiny is Abe’s-speak for a large beer. He said “Of course,” so I ordered a Tiny ice tea. (Not the Long Island variety.)
Then he asked me what I wanted to eat. There’s only one response for that at Abe’s and since they still understood what a Tiny was, I answered without ever touching a menu: “One special relleno, green, with sour cream as a neutron moderator.” He asked me if I wanted the green chile hot, mild, or half and half. Thirty years ago, I’d have ordered hot. My digestive system now has three more decade’s worth of mileage on it, so I ordered half and half. Good thing. The chile’s hotness still registered a 6 or 7 on the Abe’s 1-to-10 scale.
After I ordered, the guy with the laptop next to me said “The rellenos are still as good as they were 25 years ago.” Indeed, that’s what he was eating. The ice had broken with Abe’s hot rellenos and so we started talking. The laptop guy’s name was Scott and he maintains cellular antenna installations on towers and buildings. His company owns a lot of cell tower sites in the Denver area.
Scott is very familiar with the changes taking place in cellular infrastructure and cell-site ownership, particularly with the imminent arrival of the latest 5G gear. He told me that the electronics is migrating up the towers to be as near the antennas as possible. “All that goes up there now is 48V power and a fiber,” he said. Scott is also familiar with the migration of the electronics directly into the antennas.
It turns out that Scott is also a ham radio operator, so we talked about equipment. He’s familiar with and has repaired just about everything that’s been on the market going back to tube-based gear but he was especially impressed with the new all-digital Icom rig he now uses most of the time. Scott’s not an engineer, but hams know a ton about electronics, so we started discussing all sorts of things. He’s especially interested in the newer LDMOS power FETs. So much so that he’s lost interest in using high-voltage transmitter tubes. "Why mess with high voltage when I can get just as far with 50V?" he mused.
I was wearing my Xilinx shirt from the SC17 conference, so I took the opportunity to start talking about the very relevant Xilinx Zynq UltraScale+ RFSoC, which is finding its way into a lot of 5G infrastructure equipment. Scott hadn’t heard about it, which really isn’t surprising considering how new it is, but after I described it he said he looked forward to maybe finding one in his next ham rig.
The special relleno, green with sour cream, arrived and one bite immediately took me back three decades again. The taste had not changed one morsel. Scott and I continued to talk for an hour. Sadly, the relleno didn’t last nearly that long.
Scott and I left Abe's together. He got into his truck and I started the 15-block walk back to the convention center. The conversation and the food formed one of those really remarkable time bubbles you sometimes stumble into—and always at Abe’s.
Communications: Xilinx, for its single-chip 5G antenna interface device that dramatically reduces the size, power and complexity of traditional antenna structures.
Note: E&T is the IET's award-winning monthly magazine and associated website.
Xilinx’s Giles Peckham (center) accepts the IET Innovation Award in the Communications Category for the
Zynq UltraScale+ RFSoC from Professor Will Stewart (IET Communications Policy Panel, on left) and
Rick Edwards (Awards emcee, television presenter, and writer/comic, on right). Photo courtesy of IET.
Classifying the Xilinx Zynq UltraScale+ RFSoC device family, with its integrated multi-gigasample/sec RF ADCs and DACs, soft-decision forward error correction (SD-FEC) IP blocks, UltraScale architecture programmable logic fabric, and Arm Cortex-A53/Cortex-R5 multi-core processing subsystem as an “antenna interface device,” even a “Massive-MIMO Antenna Interface” device, sort of shortchanges the RFSoC in my opinion. The Zynq UltraScale+ RFSoC is a category killer for many, many applications that need “high-speed analog-in, high-speed analog-out, digital-processing-in-the-middle” capabilities due to the devices’ extremely high integration level, though it most assuredly will reduce the size, power, and complexity of traditional antenna structures as cited in the IET Innovation Awards literature. There's simply no other device like the Zynq UltraScale+ RFSoC on the market, as suggested by this award. (If you drill down to here on the IET Innovation Awards Web page, you’ll find that the Zynq UltraScale+ RFSoC was indeed Xilinx’s IET Innovation Awards entry in the communications category this year.)
Zynq UltraScale+ RFSoC Conceptual Diagram
The UK-based IET is one of the world’s largest engineering institutions with more than 168,000 members in 150 countries and so winning one of the IET’s annual Innovation Awards is an honor not to be taken lightly. This year, the Communications category of the IET Innovation Awards was sponsored by GCHQ (Government Communications Headquarters), the UK’s intelligence and security organization responsible for providing signals intelligence and information assurance to the UK’s government and armed forces.
For more information about the IET Innovation Awards and to see all of the various categories, click here for an animated brochure.
For more information about the Zynq UltraScale+ RFSoC, see:
The November/December 2017 issue of the ARRL’s QEX magazine carries an article written by Stefan Scholl (DC9ST) titled “The Panoradio: A Modern Software Defined Radio with Direct Sampling.” This article describes the implementation of an open-source software-defined radio (SDR) based on an Avnet Zedboard—which in turn is based on a Xilinx Zynq Z-7020 SoC—and an Analog Devices AD9467-FMC-250EBZ board based on the 16-bit, 250Msamples/sec AD9467 ADC.
Stefan Scholl’s Panoradio SDR is based on a Zedboard (the green board on the left, with a Zynq Z-7020 S0C) and an AD9467-FMC-250EBZ ADC board (the blue board on the right)
The Panoradio’s features include:
0 -100 MHz direct sampling reception
Direct sampling of 70 cm (425 – 440 MHz) signals
Three independent, zoomable waterfall displays (100 MHz to 6.1 kHz bandwidth)
Two independent audio receivers (22 kHz bandwidth) with Weaver SSB demodulation
Standalone operation (no PC needed)
Runs full Linux stack including demodulation software (e.g. Fldigi)
Beyond the comprehensive design, Scholl’s article contains one of the most concise arguments for the adoption of SDRs that I’ve seen:
“The extensive use of digital signal processing has many advantages over analog circuits: Analog processing is often limited by the laws of physics, that can hardly be overcome. Digital processing is limited only by circuit complexity—a better performance (sensitivity, dynamic range, spurs, agility, etc.) is achieved by more complex calculations and larger bit widths. Since semiconductor technology has continuously advanced following Moore’s Law, very complex systems can be built today and it is possible to achieve extraordinary accuracy and performance for digital signals with comparatively little effort.”
Scholl then lists numerous SDR advantages:
Digital FIR filters can be built with virtually any filter response.
Mixers and amplifiers implemented with digital multipliers do not introduce spurs, harmonics, or unwanted IMD (inter-modulation distortion). Gain imperfection or other parasitic behaviors are also absent.
Digital oscillators based on direct digital synthesis (DDS) achieve extremely high spectral purity with virtually no spurs or harmonics.
Digital oscillator frequency can change instantaneously without phase discontinuity.
DSP is impervious to component aging effects, impedance mismatch, and a variety of EMC issues that plague analog circuitry.
Only quantization noise is present and can be made arbitrarily low by increasing bit widths.
SDRs are easily copied and can be backed up prior to making changes so that failed experiments can be easily reversed.
The Panoradio’s DSP section consumes less than 50% of the Zynq Z-7020 SoC’s PL (programmable logic) resources. As Scholl writes: “This quite low utilization would allow for even more complex DSP.” Note that is the resource utilization in a low-end Zynq SoC. There are several Zynq SoC family members with significantly more PL resources available.
At the end of the article, Scholl writes: “Interestingly, the bottleneck is not the FFTs or the communication with the IP cores, but the drawing routines for the waterfall plots. The Zynq does not have any graphics acceleration core, which could speed up the drawing process. However, Xilinx has realized this bottleneck and included graphics acceleration in the Zynq successors: the UltraScale MPSoC, and the Zynq UltraScale+.”
(Actually, there’s just one device family here, the Zynq UltraScale+ MPSoC, with Mali-400 GPUs in the EG and EV variants, but Scholl will no doubt be even more interested in the new Zynq UltraScale+ RFSoCs, which incorporate 4Gsamples/sec ADCs and 6.4Gsamples/sec DACs—perfect for SDR applications.)
For more information on the Zynq UltraScale+ RFSoC, see:
Today, Xilinx announced plans to invest $40M to expand research and development engineering work in Ireland on artificial intelligence and machine learning for strategic markets including cloud computing, embedded vision, IIoT (industrial IoT), and 5G wireless communications. The company already has active development programs in these categories and today’s announcement signals an acceleration of development in these fields. The development was formally announced in Dublin today by The Tánaiste (Deputy Prime Minister of Ireland) and Minister for Business, Enterprise and Innovation, Frances Fitzgerald T.D., and by Kevin Cooney, Senior Vice President, Chief Information Officer and Managing Director EMEA, Xilinx Inc. The new investment is supported by the Irish government through IDA Ireland.
Xilinx first established operations in Dublin in 1995. Today, the company employs 350 people at its EMEA headquarters in Citywest, Dublin, where it operates a research, product development, engineering, and an IT center along with centralized supply, finance, legal, and HR functions. Xilinx also has R&D operations in Cork, which the company established in 2001.
Nutaq has just posted information about an intense demo where four of the company’s PicoSDR 8x8 7MHz-6GHz software-defined radio systems—based on Xilinx Virtex-6 FPGAs—are ganged to create a 32-antenna, massive-MIMO basestation that can communicate wirelessly with six UEs (user equipment systems) simultaneously. The UEs are simulated using three Xilinx ZC702 eval kits based on Zynq Z-7020 SoCs.
Nutaq’s 32-antenna massive-MIMO array
Here’s a Nutaq video of the demo:
All of the signal processing in this demo is performed on a laptop PC using Mathworks’ MATLAB, which generates waveforms for transmission by the simulated UEs and decodes received signals from the PicoSDR 8x8 receiver. As explained in the video, the transmission waveforms are downloaded to the BRAMs in the Zynq SoCs on the ZC706 boards, wirelessly transmitted to the massive-MIMO receiving antenna, captured by the PicoSDR 8x8 systems, and then sent back to MATLAB for decoding into separate UE constellations.
For more information about this demo and the PicoSDR 8x8 systems, contact Nutaq directly.
Shahriar Shahramian, department head for millimeter-Wave ASIC Research at Nokia Bell Labs, has a YouTube channel that he calls “The Signal Path” where he delivers high-quality introductory videos about many areas in electronics and deeply knowledgeable teardowns of equipment—often high-frequency equipment. (He’s been making these videos for nearly seven years.) His teardown videos often uncover Xilinx All Programmable devices inside the equipment he studies, and this blog is about just such an instrument: the $2595 Siglent SSA3032X 9kHz - 3.2GHz Spectrum Analyzer and Tracking Generator (SA and TG).
Siglent SSA3032X 9kHz - 3.2GHz Spectrum Analyzer and Tracking Generator
A recently published teardown video by Shahramian shows you how the Siglent SSA3032X SA and TG is designed and how it works. In this 1-hour video, you get a detailed look inside of the Siglent SSA3032X SA and TG, Shahramian’s analysis of how the instrument is designed, extended demonstrations of its performance while conducting myriad RF tests, and a very good look at the components used in the instrument’s design.
While examining the instrument’s digital board, Shahramian points out a Xilinx Spartan-6 LX45 FPGA (at 8:40 in the video). Based on its physical location, he concludes that the FPGA is used for real-time control of the SA’s analog sections and ADC, graphics and control of its large 1024x600-pixel LCD, and monitoring of the instrument’s front-panel controls. The FPGA acts as the Spectrum Analyzer’s real-time control master, working in tandem with the on-board TI Sitara microprocessor, which is based on an ARM Cortex-A8 microprocessor.
The digital board for the Siglent SSA3032X 9kHz - 3.2GHz Spectrum Analyzer and Tracking Generator uses a Xilinx Spartan-6 FPGA for real-time instrument control and management
If you have the time, the video is well worth watching:
By the way, if you like Shahramian’s videos, one way you can help him is to let vendors like Siglent know you watched this video to learn about the company’s SSA3032X.
On Monday, a SpaceX Falcon 9 rocket launched from Vandenberg Air Force Base in California successfully placed ten more Iridium NEXT communications satellites into low-earth orbit (LEO). This is the third such Iridium launch for SpaceX, which means that the company has placed 30 of the planned 75 Iridium NEXT comsats into LEO. (There will be 81 Iridium satellites in the completed constellation.) Each of the ten Iridium NEXT satellites in this launch incorporates several Xilinx space-grade Virtex-5QV FPGAs used to implement the satellites’ On Board Processor (OBP) hardware developed by SEAKR Engineering. (Space-grade Virtex-5QV FPGAs are the radiation-hardened version of commercial Xilinx Virtex-5 FPGAs and were developed under sponsorship by AFRL's Space Vehicles Directorate.)
SpaceX has posted a YouTube video of the launch that lasts 90 minutes, but assuming you don’t have time for that, here’s a 6-minute version from SciNews that starts with a 10-second countdown and ends with the successful recovery of the Falcon 9 rocket’s first stage on the landing droneship named “Just Read the Instructions”:
LightReading has just posted a 5-minute video interview with Kirk Saban (Xilinx’s Senior Director for FPGA and SoC Product Management and Marketing) discussing some of the aspects of the newly announced Zynq UltraScale+ RFSoCs with on-chip RF ADCs and DACs. These devices are going to revolutionize the design of all sorts of high-end equipment that must deal with high-speed analog signals in markets as diverse as 5G communications, broadband cable, test and measurement, and aerospace/defense.
--“Revolution” written by John Lennon and Paul McCartney
Today, Xilinx announcedfive new Zynq UltraScale+ RFSoC devices with all of the things you expect in a Xilinx Zynq UltraScale+ SoC—a 4-core APU with 64-bit ARM Cortex A-53 processor cores, a 2-core RPU with two 32-bit ARM Cortex-R5 processors, and ultra-fast UltraScale+ programmable logic—with revolutionary new additions: 12-bit, RF-class ADCs, 14-bit, RF-class DACs, and integrated SD-FEC (Soft Decision Forward Error Correction) cores.
Just in case you missed the plurals in that last sentence, it’s not one but multiple RF ADCs and DACs.
That means you can bring RF analog signals directly into these chips, process those signals using high-speed programmable logic along with thousands of DSP48E2 slices, and then output processed RF analog signals—using the same device to do everything. In addition, if you’re decoding and/or encoding data, two of the announced Zynq UltraScale+ RFSoC family members incorporate SD-FEC IP cores that support LDPC coding/decoding and Turbo decoding for applications including 5G wireless communications, backhaul, DOCSIS, and LTE. If you’re dealing with RF signals and high-speed communications, you know just how revolutionary these parts are.
For everyone else not accustomed to handling RF analog signals… well you’ll just have to take my word for it. These devices are revolutionary.
Here’s a conceptual block diagram of a Zynq UltraScale+ RFSoC:
Here’s a table that shows you some of the resources available on the new Zynq UltraScale+ RFSoC devices:
As you can see from the table, you can get as many as eight 12-bit, 4Gsamples/sec ADCs or sixteen 12-bit, 2Gsamples/sec ADCs on one device. You can also get eight or sixteen 14-bit, 6.4Gsamples/sec DACs on the same device. Two of the Zynq UltraScale+ RFSoCs also incorporate eight SD-FECs. In addition, there are plenty of logic cells, DSP slices, and RAM on these devices to build just about anything you can imagine. (With my instrumentation background, I can imagine new classes of DSOs and VSTs (Vector Signal Transceivers), for example.)
You get numerous benefits by basing your design on a Zynq UltraScale+ RFSoC device. The first and most obvious is real estate. Putting the ADCs, DACs, processors, programmable logic, DSPs, memory, and programmable I/O on one device saves a tremendous amount of board space and means you won’t be running high-speed traces across the pcb to hook all these blocks together.
Next, you save the complexity of dealing with high-speed converter interfaces like JESD204B/C. The analog converters are already interfaced to the processors and logic inside of the device. Done. Debugged. Finished.
You also save the power associated with those high-speed interfaces. That alone can amount to several watts of power savings. These benefits are reviewed in a new White Paper titled “All Programmable RF-Sampling Solutions.”
This week, EXFO announced and demonstrated its FTBx-88400NGE Power Blazer 400G Ethernet Tester at the ECOC 2017 optical communications conference in Gothenburg, Sweden using a Xilinx VCU140 FPGA design platform as an interoperability target. The VCU140 development platform is based on a Xilinx Virtex UltraScale+ VU9P FPGA. EXFO’s FTBx-88400NGE Power Blazer offers advanced testing for the full suite of new 400G technologies including support for FlexE (Flex Ethernet), 400G Ethernet, and high-speed transceiver validation. The Flex Ethernet (FlexE) function supports one or more bonded 100GBASE-R PHYs supporting multiple Ethernet MAC operating at a rate of 10, 40, or n x 25Gbps. Flex Ethernet is a key data center technology that helps data centers deliver links that are faster than emerging 400G solutions.
Here’s a photo of the ECOC 2017 demo:
This demonstration is yet one more proof point for the 400GbE standard, which will be used in a variety of high-speed communications applications including data-center interconnect, next-generation switch and router line cards, and high-end OTN transponders.
Last September at the GNU Radio Conference in Boulder, Colorado, Ettus Research announced the RFNoC & Vivado Challenge for SDR (software-defined radio). Ettus’ RFNoC (RF Network on Chip) is designed to allow you to efficiently harness the latest-generation FPGAs for SDR applications without being an expert firmware or FPGA developer. Today, Ettus Research and Xilinx announced the three challenge winners.
Ettus’ GUI-based RFNoC design tool allows you to create FPGA applications as easily as you can create GNU Radio flowgraphs. This includes the ability to seamlessly transfer data between your host PC and an FPGA. It dramatically eases the task of FPGA off-loading in SDR applications. Ettus’ RFNoC is built upon Xilinx’s Vivado HLS.
Here are the three winning teams and their projects:
Novator Solutions recently licensed RFEL’s ChannelCore Flex RF channelizer IP for the heart of its NCR-2000 Channelizer server, which is built from a crate full of National Instruments (NI) PXIe modules. Using RFEL’s ChannelCore Flex RF channelizer IP, which is instantiated on NI’s PXIe-7975R FlexRIO FPGA module (based on a Xilinx Kintex-7 XC7K410T FPGA), Novator’s NCR-2000 Channelizer server can analyze thousands of RF signals with a single receiver. Ideally you’d dedicate one receiver to every signal (or RF channel) of interest. However, as the number of channels increases, that approach rapidly becomes impractical both physically and because of cost considerations. Instead, you use a channelizer.
Here’s a block diagram of Novator Solutions’ NCR-2000 Channelizer server:
Novator Solutions’ NCR-2000 Channelizer server block diagram
The channelizer IP running on the FPGAs at the heart of the NCR-2000 Channelizer server are based on RFEL’s ChannelCore Flex IP, which can discriminate thousands of independently defined channels across any RF bandwidth in real time. Channel parameters that can be specified to an accuracy of better than 0.06 Hz.
Here’s a block diagram of RFEL’s ChannelCore Flex channelizer IP:
RFEL’s ChannelCore Flex channelizer IP block diagram
One key thing to note here is that this channelizer IP supports multiple inputs from multiple RF receivers. The IP block can accommodate as many as 16 inputs and dedicates separate FPGA coarse-stage resources to each input. Input parallelism can range from 1 to 16 coarse stages. With 16x input parallelism, a single ChannelCore Flex IP core can simultaneously process more than 50GHz of RF bandwidth.
There’s a lot of 5G research already taking place at National Instruments’ (NI’s) new 5G Innovation Lab located in Austin, Texas (announced in May) and RCR Wireless News’ Martha DeGrasse recently published a report about the lab on the publication’s Web site. In this 5G Innovation Lab, NI’s proprietary T&M equipment and software are being used by carriers, chipmakers, and equipment vendors including AT&T, Verizon, Ericsson, and Intel to develop and test 5G hardware and protocols.
One of the research projects DeGrasse describes involves Verizon’s 5GTF—V5GTF, the Verizon 5G Technology Forum—which is developing a 28/39GHz wireless communications platform designed to replace fiber in fixed-wireless applications. There’s a running demo of this technology in the NI 5G Research Lab that uses a 28GHz link to convey a 3Gbps digital stream between a simulated basestation and a simulated fixed-location user device. Here’s a brand new, 2-minute video of a demo:
The equipment used in this V5GTF demo includes NI’s mmWave Transceiver System which includes FPGA processing modules based on Xilinx Virtex-7 and Kintex-7 FGPAs. The FPGA processing modules handle the complex, still-in-development modulation and control protocols being developed for mmWave communications.
It’s essentially a solid block of raw SDR capability jammed into a compact, 55W (typ) package. This programmable powerhouse has the RF and processing capabilities you need to develop large, advanced digital radio systems using development tools from VadaTech, Analog Devices, and Xilinx. The AMC597 is compatible with Analog Devices’ design tools for AD9371; you can develop your own FPGA-based processing configuration with Xilinx’s Vivado Design Suite and System Generator for DSP; and VadaTech supplies reference designs with VHDL source code, documentation, and configuration binary files.
This new article gets into many specifics with respect to designing the RFSoC into systems with block diagrams and performance numbers. In particular, there’s a table showing MIMO radio designs based on the RFSoC with 37% to 51% power reductions and significant pcb real-estate savings due to the RFSoC’s integrated, multi-Gbps ADCs and DACs.
If you’re looking to glean a few more technical details about the RFSoC, this article is the latest place to go.
There’s considerable 5G experimentation taking place as the radio standards have not yet gelled and researchers are looking to optimize every aspect. SDRs (software-defined radios) are excellent experimental tools for such research—NI’s (National Instruments’) SDR products especially so because, as the Wireless Communication Research Laboratory at Istanbul Technical University discovered:
“NI SDR products helped us achieve our project goals faster and with fewer complexities due to reusability, existing examples, and the mature community. We had access to documentation around the examples, ready-to-run conceptual examples, and courseware and lab materials around the grounding wireless communication topics through the NI ecosystem. We took advantage of the graphical nature of LabVIEW to combine existing blocks of algorithms more easily compared to text-based options.”
Researchers at the Wireless Communication Research Laboratory were experimenting with UFMC (universal filtered multicarrier) modulation, a leading modulation candidate technique for 5G communications. Although current communication standards frequently use OFDM (orthogonal frequency-division multiplexing), it is not considered to be a suitable modulation technique for 5G systems due to its tight synchronization requirements, inefficient spectral properties (such as high spectral side-lobe levels), and cyclic prefix (CP) overhead. UFMC has relatively relaxed synchronization requirements.