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Xcell Daily Blog (Archived) - Page 2

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Xcell Daily Blog (Archived) - Page 2

Xilinx Employee
Xilinx Employee

The penalty for the Internet’s ability to ship packets anywhere on the planet (and off-planet) is overhead and one of the largest chunks of overhead is the TCP/IP stack. For most applications, we ignore the TCP/IP latency tax but for high-speed financial trading, where microseconds of delay translate into costs measured in millions of dollars, reducing TCP/IP overhead is worth a lot. The need to minimizeTCP/IP latency creates a niche for TCP/IP offload engines and FPGAs play a big role here. TCP Offload Engines (TOE) developed by the Dini Group and built from the configurable hardware on the Dini Group’s DNPCIe_40G_KU_LL PCIe board based on a Xilinx 20nm Kintex UltraScale KU040 FPGA have the ability to achieve the theoretical minimum Ethernet packet-processing latency at 10G and 40G Ethernet line rates. (See “DINI Group Announces Immediate Availability of Kintex UltraScale FPGA Board.”)

 

The following demo video, shot at the recent OFC 2015 conference in Los Angeles, shows a Dini Group DNPCIe_40G_KU_LL board running six Dini Group TOE128 TCP offload engines instantiated and running inside the board’s Kintex UltraScale KU040 FPGA.

 

 

 

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Xilinx Employee
Xilinx Employee

The ONetSwitch Kickstarter project, an open-source SDN platform based on a Xilinx Zynq SoC, just finished a successful funding campaign, passing its $50K funding goal just 24 hours before the end of the campaign. (See “An Open Source Kickstarter SDN project based on Zynq? For $649? Wowzers!”) The ONetSwitch platform is designed to allow you to write Linux software applications to achieve all sorts of network functions such as NAS, VPN, and Firewall. The Kickstarter campaign collected $53,769 in pledges from 119 backers. The project was undertaken by a company called MeshSr.

 

 

ONetSwitch Board Photo 2.jpg

 

 

For more information there’s a:

 

Getting Started Guide

Hardware Users guide

Workflow Guide

Reference Design Guide

 

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Xilinx Employee
Xilinx Employee

Sumitomo Electric’s 4x25G QSFP28 LR4 optical module supports fiber links as long as 10km. This OFC 2015 video shows a Xilinx Virtex UltraScale FPGA driving one of these modules and 10km of optical fiber. The QSFP28 has the same footprint as a 40G QSFP+ optical module but it employs four 25Gbps lanes through an upgraded electrical interface. When compared to the alternatives, 100G QSFP28 increases density and decreases both power and price/bit, which is why it is fast becoming the universal form factor for data center optics.

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Xilinx Employee
Xilinx Employee

Martin Gilpatric from Xilinx, who either cannot or will not make a bad video, takes all of 90 seconds in a video from OFC 2015 to fully explain the demo of a Virtex UltraScale FPGA on a VCU109 board driving a Finisar 100G ER4f CFP4 optical module connected to 50km of optical fiber—with no transmission errors. The ER4f spec includes a noise floor that requires the use of an RS-FEC to guarantee error-free transmission. The demo has a Xilinx 100G RS-FEC LogiCORE IP working in conjunction with the embedded, hard-core 100G Ethernet MAC in the Virtex UltraScale FPGA and, sure enough, the 50km link is running error-free.

 

 

 

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Xilinx Employee
Xilinx Employee

This short, 90-second video from OFC 2015 shows a Xilinx Virtex UltraScale VU095 FPGA driving a 4x25G TE Connectivity QSFP28 SR4 4-channel optical transceiver connected to 100m of fiber. The remarkable thing about this transceiver is its low power consumption: 1.5W per end.

 

 

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Xilinx Employee
Xilinx Employee

It’s hard to believe you can hear nearly half a dozen different high-speed I/O protocols named in a short 90-second video but OTN System Engineer Ian McBryan from Xilinx manages to name 2x100G OTN, OTL 4.4, a CFP4 optical module, Interlaken, and CAUI-4—all running on a 20nm Virtex UltraScale VU095 FPGA. What’s the point? The extreme, high-speed I/O programmability and flexibility of Virtex UltraScale devices.

 

 

 

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Xilinx Employee
Xilinx Employee

As FPGAs get bigger, many systems start to fit into just one programmable device.

 

But not all.

 

For a variety of reasons, some really large systems must still be implemented with multiple devices, which elevates the system-level importance of efficient, fast chip-to-chip interconnect. With the rise of multi-Gbps SerDes ports, the scalable Interlaken protocol has become a de facto standard for chip-to-chip interconnect over the past decade, especially in the networking arena. Xilinx has supported the use of the Interlaken protocol over multiple FPGA generations, previously as a soft core. All Virtex UltraScale devices and some Kintex UltraScale devices now incorporate multiple embedded hard 150Gbps Interlaken IP cores—using 12x12.5Gbps or 6x25Gbps lanes—which makes it even easier for you to use this efficient, highly standardized chip-to-chip protocol.

 

The following 4-minute video gives you a quick overview of this aspect of the UltraScale architecture. The video in the demo shows a Virtex UltraScale VU095 All Programmable device mounted on a VCU107 Eval Board running 12 Interlaken lanes at 12.5Gbps for an aggregate peak bandwidth of 150Gbps using only 12 differential pairs. Here’s a block diagram of the system in the demo:

 

 

UltraScale Interlaken Demo Block Diagram.jpg

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Xilinx Employee

The new 3.5-minute video below demonstrates the hot-swap ability of the hard, integrated 100G Ethernet MAC in Xilinx 20nm Virtex UltraScale FPGAs, which incorporate multiple hard 100G Ethernet MACs and the 30.5Gbps GTY SerDes ports needed for the job. The demo shows a Virtex UltraScale VU095 FPGA on a VCU107 Eval Board automatically switching from a 10x10G configuration to a 4x25G configuration as Xilinx Transceiver Technical Marketing Manager Martin Gilpatric first plugs a 10x10G CFP2 SR10 optical module into the board and then hot swaps that module for a 4x25G CFP2 LR4 optical module.

 

The test configuration in the Virtex UltraScale VU095 FPGA looks like this:

 

 

UltraScale 100G Ethernet Demo Block Diagram.jpg

 

 

The blue MDIO block in the FPGA senses the module type and then the FPGA automatically adapts the 100G Ethernet MAC accordingly.

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Xilinx Employee

On display at OFC 2015 a couple of weeks ago and now formally announced, JDSU has rolled out its pre-standard ONT 400G Ethernet test platform based on Xilinx 20nm UltraScale All Programmable devices. The new test platform employs JDSU’s successful ONT test platform architecture, which pioneered the concept of comprehensive module stress testing using less test equipment. The 400G Ethernet standard is currently in flux and JDSU required a reliable implementation technology that could simultaneously support the evolution of the 400G Ethernet standard and of JDSU’s growing product line. That’s why JDSU engineers selected the 20nm UltraScale FPGAs: because these devices have the speed and SerDes ports required to support 400G development with the needed flexibility to keep up with the evolving and future standards. Perhaps your high-speed networking project has similar needs.

 

Seeing is believing, however. It’s one thing to announce that such a leading-edge product exists in a press release. It’s quite another to show the working demo running on real hardware, so here’s the proof-of-existence video from OFC 2015:

 

 

 

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Xilinx Employee

The following 2.5-minute video from OFC 2015 shows a Xelic XCO4EFECSC 100G Staircase EFEC (Enhanced FEC) IP core for OTN interoperating with a Cortina 100G FEC chip in a CS605x Evaluation System, monitored by a JDSU tester. The Xelic IP core shown in the demo is implemented on a Xilinx Virtex-7 VC730 3D IC OTN target platform board but Xelic has already optimized the core for the UltraScale architecture and the company was able to use the UltraScale architecture’s enhanced on-chip DSP resources to reduce the core’s LUT count below 100K—a relatively small portion of even the smallest Xilinx Virtex UltraScale device—which represents a significant reduction in the use of on-chip programmable logic resources.

 

 

 

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Xilinx Employee

The following short, 1-minute video from OFC 2015 shows a Xilinx Virtex UltraScale VU095 FPGA on a VCU107 Eval Board implementing a 4x25G connection, directly driving 3m of direct attached copper cable to a 4-port IXIA 25G Load Module. There are four low-latency 25G Ethernet MACs conforming to the 25G Ethernet Consortium’s spec implemented in the VU095 FPGA. The demo shows long-term, error-free operation of the 4x25G implementation.

 

 

 

 

 

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Xilinx Employee

The following 3-minute video shows a working demo of IP Light’s new Mobile Fronthaul (MFH) IP that packages CPRI streams from remote radio heads (RRHs) and maps them into OTU2r containers for transmission over OTNs (Optical Transport Networks) to centralized baseband units (BBUs) using the new ITU-T SG15 TD 289 specs for mobile fronthauling. CPRI is the digital interface standard for mobile base station analog front ends. OTN is the existing, high-speed optical infrastructure for long-distance digital communications. CPRI over OTN is one promising approach to fronthauling that can make C-RANs (Cloud or Centralized Radio Area Networks) possible. IP Light’s MFH IP is shown running on a Xilinx Kintex-7 FPGA at OFC 2015.

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Xilinx Employee

The 5-minute video below shows two interoperability demos between Ixia’s JumpStart Test Systems and Xilinx UltraScale FPGA Eval Boards. The first demo in the video is for 4x25G Ethernet, a rapidly evolving technology for data centers that’s designed to instantly boost the total data center internal bandwidth. According to Charles Seifert, Senior Product Manager at Ixia, this is the first multivendor interoperability demo for 4x25G Ethernet (because interoperating with yourself is just not that exciting).

 

The second demo uses Ixia’s JumpStart Test System, a 4-port CFP4 100G Ethernet load module with its four 100G ports used as fiber transports to exchange 400G Ethernet streams with another Xilinx UltraScale Eval Board. There are two 400GE MAC engines from different vendors talking to each other in this demo. A small but important part of the demo: the transmission and reception are error-free.

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Xilinx Employee

 

(Excerpted and adapted from the latest issue of Xcell Journal)

 

By Lei Guan, Member of Technical Staff, Bell Laboratories, Alcatel Lucent Ireland

 

To test the thermal properties of optical modules, engineers traditionally had two choices. They could use a complicated network data generator to create high-speed (10-Gbps) links and then test the thermal properties of the optical modules; or they could utilize a so-called “thermal-equivalent” module with preset tunable voltage and current to mimic the thermal situation and evaluate the thermal properties without using any real high-speed data. Neither of these approaches is optimal. The first approach is a costly operation due to the need for a professional highspeed network data generator, while the second method is too abstract. A thermal-equivalent module cannot fully reflect the temperature variation driven by the physical switching behavior.

 

The fundamental requirement of this type of thermal testing is to stimulate the XFP optical transceiver continuously with 10Gbps data while using an IR camera to track and characterize the temperature variation. I picked the Xilinx ZC706 evaluation board as the development host, because the GTX transceivers on the main device, the Zynq-7000 SoC XC7Z045 (speed grade -2), can easily achieve single-line 10Gbps data transmission.

 

I’ve found over the course of my seven years of doing FPGA development that you can significantly reduce your design cycle by using as many Xilinx cores as possible. In this design, I kept the same strategy and started from the Integrated Bit Error Ratio (IBERT) core, which you can utilize to perform pattern generation and verification to evaluate the GTX transceivers on the Zynq SoC. Then, in order to properly route the design, I created a phase-aligned clock-distribution unit based on the Mixed-Mode Clock Manager (MMCM) core for simultaneously clocking both of the GTX transceivers on the FPGA fabric and the optical transceiver on the XFP evaluation board. Figure 1 shows the system diagram.

 

 

ZC706-Based 10Gbps Optical Module Tester.png

 

Figure 1: Block Diagram of the Zynq-Based Hot Optical Module Test System

 

 

By using Xilinx cores, together with the ZC706 evaluation board, it’s easy to build a test platform for evaluating high-speed optical transceivers. In this design, we illustrated the evaluation of a single XFP module. However, you can straightforwardly apply the design methodology to quickly build a logic core for testing multiple optical transceiver modules.

 

This blog is an excerpt. To read the full article in the latest issue of Xcell Journal, click here.

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The Coherent Accelerator Processor Interface (CAPI) on IBM POWER8 server systems allows solution architects to improve system-level performance by connecting custom acceleration engines to the coherent fabric of the POWER8 multicore processor chip, which results in a simple programming paradigm while delivering performance well beyond today's I/O-attached acceleration engines. Convey Computer announced an initial version of its CAPI Development Kit based on its Eagle PCIe coprocessor board at last week’s Open Power Summit held in Silicon Valley. The PCIe Eagle coprocessor/hardware accelerator combines a Xilinx Virtex-7 980T FPGA with a large amount of on-board memory (16 or 32 Gbytes, 16Gbytes included in the CAPI Development Kit). The board dissipates only 75W.

 

CAPI relies on a Power Service Layer (PSL) loaded in the coprocessor FPGAs to provide address translation and caching for the hardware accelerator. A Coherent Accelerator Processor Proxy (CAPP) in the POWER8 chip participates directly in the POWER8 coherency protocols on behalf of the coprocessor, ensuring a consistent view of memory within the virtual address space. To a program running on a Power8 processor, access looks like a thread running on the host processor. Here’s a simple diagram showing the link between the IBM Power8 multicore processor and the Convey Eagle Accelerator.

 

 

Power8 CAPI.jpg

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Xilinx Employee

Three high-speed networking demos in the Xilinx booth (#729) at next week’s OFC 2015 in Los Angeles highlights the abilities of Xilinx UltraScale FPGAs and IP to implement 100G and 400G systems with one chip. The demos include:

 

  • A Xilinx Virtex UltraScale VU095 All Programmable device loaded with pre-standard 400GE MAC and PCS IP will be connected to four Sumitomo Electric CFP4 LR4 modules, communicating with a JDSU ONT 400GE Optical Network Tester with four sets of JDSU LR4 modules.

 

  • A low-latency 4x25G Ethernet MAC demo, based on a Virtex UltraScale VCU107 board, shows four channels of 25G Ethernet operating over 3M of direct-attached copper cable from a QSFP28 module plugged into the VCU107 board and connected to Ixia's Xcellon-Multis QSFP28 100/4x25GE load module. The Xilinx low-latency 25G Ethernet MAC used in this demo supports the 25G Ethernet Consortium’s specification and will support the future IEEE 25GE specification. (There’s a related presentation on Wednesday, March 25 in the Expo Theater titled “Test 400GE and 25GE Network Equipment Quickly, Efficiently, and Accurately—Pick any Three” by Thananya Baldwin, Senior Director of Strategic Programs at Ixia and Gilles Garcia, Director of Wired Communication at Xilinx.)

 

  • A Xilinx Virtex UltraScale VU095 device implementing a 2x100G OTN switching application. There’s an upgrade path to 4/5x100G OTN switching using a larger Virtex UltraScale VU190 device. (You might also want to attend the related presentation on Wednesday, March 25 in the Expo Theater titled “Enable Your 500G/1T OTN Line Card Today with All Programmable FPGAs” by David Yeh, OTN Product Marketing Manager at Xilinx.)

 

If you’d like to hear an overview covering the use of advanced All Programmable devices to implement high-performance networking hardware including SDN equipment, you might want to attend Gordon Brebner’s two presentations at OFC. The first, presented on Monday, March 23 in Room 408B, is titled “Programmable Hardware in Software Defined Networking” and the second, on Thursday, March 26 in Room 410, is titled “Programmable Hardware for High Performance SDN. Gordon is a Distinguished Engineer at Xilinx.

 

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Xilinx Employee

With OFC 2015 in Los Angeles coming up next week, this is the week for a focus on high-speed optical communications. In addition to the 100G Reed-Solomon FEC IP block announcement from Xilinx that I covered earlier today, here’s a just-posted, 3.5-minute video demo of 100G optical Ethernet modules operating with a Xilinx Virtex UltraScale VU095 FPGA, which incorporates a hardened-core 100G Ethernet MAC. The demo, narrated by Technical Marketing Manager Martin Gilpatric with his usual crystal clarity and a minimal amount of marketing schmaltz, shows hot swapping of 10x10G and 4x25G optical modules while the 100G Ethernet IP implementation keeps pace.

 

 

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Xilinx Employee

FECs are one of those unique elements in the electronics world. Two truths about FECs:

 

 

1. If you don’t know what a FEC is, you probably don’t need one.

 

2. If you know what a FEC is, you probably need one.

 

 

(A FEC is a Forward Error Correction block)

 

Xilinx has just announced a low-latency 100G IEEE 802.3bj Reed-Solomon FEC (RS-FEC) as a LogiCORE IP block for high-speed, 100G Ethernet communications over optical media using standards including SR4, CWDM4, PSM4, or ER4f. There’s also a reference design with the FEC block integrated with other 100G Ethernet IP. Xilinx will be demonstrating this 100G RS-FEC implemented with a Xilinx Virtex UltraScale VU095 FPGA and operating with optics from Finisar (in the Ethernet Alliance booth #2531) and TE Connectivity (booth #1417) at OFC 2015 in Los Angeles later this month.

 

 

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(Excerpted and adapted from the latest issue of Xcell Journal)

 

By Paul Dillien and Tom Kean, PhD

 

An obvious tactic for protecting information is to encrypt data as it transits the network and moves around the data center. Encryption ensures that, should the data be intercepted by an unauthorized party sniffing the link, it cannot be read. Ideally, too, the data should be authenticated to ensure its integrity. Message authentication is designed to detect where the original encrypted data has been altered, either by means of a transmission error or from being maliciously tampered with by an attacker seeking to gain an advantage.

 

The popularity of the Ethernet standard has driven down costs, making it even more attractive, and this virtuous circle ensures the continuance of Ethernet as the Layer 2 technology of choice. However, up until a few years ago, the specification did not include any encryption, leaving the job to technologies such as IPsec that operate in the upper layers of the communications protocol stack.

 

Now, a new extension to Ethernet adds a raft of security measures, under the specification IEEE 802.1AE. Specified a few years ago, this technology features an integrated security system that encrypts and authenticates messages while also detecting and defeating a range of attacks on the network. The specification is known as the Media Access Control Security standard, or more commonly as MACsec, and Algotronix set out several years ago to produce IP cores that provide hardware-accelerated encryption over a range of data rates. (Algotronix also supplies an intellectual-property core for IPsec that has a very similar interface to the MACsec product and would be a good choice in systems that need to support both standards.)

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Xilinx Employee

(Excerpted and adapted from the latest issue of Xcell Journal)

 

By John Kilpatrick and Robbie Shergill (Analog Devices), and Manish Sinha (Xilinx)

 

The ever-increasing demand for data on the world’s cellular networks has operators searching for ways to increase the capacity 5,000-fold by 2030. Getting there will require a 5x increase in channel performance, a 20x increase in allocated spectrum and a 50x increase in the number of cell sites. Many of these new cells will be placed indoors, where the majority of traffic originates, and fiber is the top choice to funnel the traffic back into the networks. But there are many outdoor locations where fiber is not available or is too expensive to connect, and for these situations wireless backhaul is the most viable alternative.

 

Unlicensed spectrum at 5GHz is available and does not require a line-of-sight path. However, the bandwidth is limited and interference from other users of this spectrum is almost guaranteed due to heavy traffic and wide antenna patterns. Communication links of 60GHz are emerging as a leading contender to provide these backhaul links for the many thousands of outdoor cells that will be required to meet the capacity demands. This spectrum is also unlicensed, but unlike frequencies below 6GHz, it contains up to 9GHz of available bandwidth. Moreover, the high frequency allows for very narrow and focused antenna patterns that are somewhat immune to interference.

 

A complete 60-GHz two-way data communication link developed by Xilinx and Hittite Microwave (now part of Analog Devices) demonstrates superior performance and the flexibility to meet the requirements of the small-cell backhaul market (Figure 1). Xilinx developed the digital modem portion of the platform and Analog Devices, the millimeter-wave radio portion.

 

 

60GHz Backhaul Comm Link Block Diagram.jpg

 

 

Figure 1 – High-level block diagram of the complete two-way communication link

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Xilinx Employee

The eagerly anticipated latest issue of the Xilinx Xcell Journal is now online and available. In addition to the cover story on the introduction of the three new Xilinx 16nm UltraScale+ All Programmable device families, this issue includes in-depth articles about:

 

  • The Solar Orbiter
  • 60G Millimeter-Wave Backhaul
  • Data Center Security
  • The Zynq SoC (two articles)
  • PetaLinux
  • Algorithm Refactoring

 

Along with announcements from Xilinx and its Alliance Program members.

 

Click here for more info.

 

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Back on November 18th, ZTE announced that the company successfully completed pre-commercial field testing of the world's first pre5G 3D/Massive MIMO (Multiple-Input Multiple-Output) base stations in partnership with China Mobile. Tests showed the 64-port/128-antenna base station provides excellent coverage enhancement in complicated multi-path urban environments, indoor areas, and open rural spaces as well—further demonstrating the technology’s superiority of the over existing intelligent antennas. Dr. Xiang Jiying, CTO of ZTE’s Wireless Division, said “As the number of antennas is ten times more, 3D/Massive MIMO had appeared to be a distant pipe-dream. However, the test indicates that we are taking a big step forward to realize the new technology using 4G handsets. This is a result of a number of innovations, and is in line with the pre5G concept previously proposed by ZTE. We will continue to deliver Pre5G features to offer 5G-like experience before 5G standardization.”

 

Today, Xilinx announced that ZTE's pre5G 3D/massive MIMO base station is based on the company’s Kintex-7 All Programmable FPGAs, used in conjunction with ZTE's high-performance vector processor SoCs. "Together, our pre5G multi-user/multi-stream spatial multiplexing technology and Xilinx-7 series FPGAs are enabling our base station to set new records in single-carrier transmission capacity and spectral efficiency," said Dr. Xiang.

 

 

 

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If you’re involved with the design of cellular systems you’ve at least heard of CloudRANs (CRANs) and Fronthauling, the technologies you need to make better, more cost-effective use of widely distributed processing power. Raghu Rao, Xilinx Principal Architect of Wireless Communications, put together a tutorial on the topic, which he presented live. Now he’s put the tutorial on video and you can watch it for free. No registration needed. The video appears below:

 

 

 

 

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MegaBEE Logo.jpgThe “M”s in MIMO stand for “multiple” but a MIMO antenna array with 256x256 antennas is “massive” in anyone’s book. Prototyping large 5G MIMO systems is going to be a challenge—one that the Zynq-based MegaBEE prototyping platform from BEEcube intends to simplify. The Xilinx Zynq SoC's dual-core ARM Cortex-A9 MPCore processor runs a Linux cluster architecture unique in the 5G prototyping space. The MegaBEE has built-in capabilities for 8x8 MIMO applications with easy scalability to 16x16, 32x32, 64x64, 128x128, or 256x256 MIMO antenna configurations using the MegaBEE platform’s integrated RF chains, filters, and power amps. The platform also incorporates 4000 DSP48 slices and multiple 10GE ports provided by Xilinx Virtex-7 FPGAs with on-board DDR3 SDRAM for storing real-time 5G test vectors.

 

“The MegaBEE platform delivers all the required elements for 5G massive MIMO prototyping in one box,” says BEEcube founder and CEO Chen Chang. The MegaBEE platform's clocking structure allows antenna modules to be dispersed over a three mile radius while maintaining phase coherence, enabling the system to be used for developing prototype systems using distributed MIMO as well as massive MIMO.

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You can use a Xilinx Zynq-7000 SoC to implement a complete wireless backhaul network node, as demonstrated in the reference design found in the new 31-page Xilinx White Paper WP457 “Integrated Single System-on-a-Chip Mobile Backhaul for Small-Cell Deployments.”

 

One Zynq-7000 device can:

 

  • Run the application software on the Zynq SoC’s dual-core ARM Cortex-A9 MPCore processor.
  • Implement the backhaul functionality—including timing and synchronization, packet switching, and the wireless modem—using the Zynq SoC’s Programmable Logic (PL).
  • Implement the required interfaces, including 1 GbE and 10 GbE MAC/PCS interfaces, and interfaces to ADCs and DACs using JESD204B or LVDS using the Zynq SoC’s SerDes and programmable I/O ports.

 

Here’s a block diagram of the design:

 

 

Zynq Backhaul Modem Reference Design.jpg

 

 

And here’s a diagram from the White Paper showing you how the wireless backhaul tasks are distributed to the on-chip ARM Cortex-A9 processor cores and the programmable logic:

 

 

Zynq Backhaul Modem Task Distribution.jpg

 

The White Paper covers many details including the design of an E-band Modem reference design. Download it here.

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David Squires of BEEcube and David Hawke of Xilinx have just published an article on the EETimes Web site titled “5 Years to 5G: Enabling Rapid 5G System Development.” The article lays out some of the challenges of the 5G RAN and ways in which ideas can be implemented in hardware -- both for prototyping, which needs to happen over the next three years, and ultimately for production deployment, which is slated to commence in 2020. If things go as planned, 5G will provide 1000x more capacity and will support 100+ billion connections with data rates to 10Gbps and less than 1msec latency. Those are goals we’d all like to see realized.

 

Developing 5G networks that meet these goals will require a combination of existing systems such as LTE-Advanced and WiFi, combined with revolutionary technologies designed to support new uses such as the Internet of Things (IoT), augmented reality, immersive gaming, and UHD (ultra-high-definition) streaming video. 5G will see some of the spectrum below 6GHz being re-purposed for use with newer technologies and existing cellular bands will be augmented with new spectrum allocations above 6GHz.

 

If you’d like a detailed look at the future of 5G communications, take a read. As one EETimes reader commented, “This is really comprehensive!”

 

 

 

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SDR (Software Defined Radio) is the wireless Holy Grail and Cambridge Consultants will be demonstrating the newest success in reaching that goal at Mobile World Congress (MWC) 2015 in Barcelona next month. The company’s Pizzicato technology “can achieve 3 Gbits/second digital output at up to 1.5 GHz while consuming less than 300 mW and delivering up to 1mW to the antenna,” according to an EETimes article by Jessica Lipsky. The article also states: “a core and software for an all-digital radio transmitter that could cost less than $1.” However, that’s with the technology embodied in a 28nm ASIC. The technology will be embedded in a Xilinx FPGA at next month’s MWC 2015 demo. According to the EETimes article, “The demonstrator is able to emulate 14 basestations with a single signal, running at 900 MHz for 2G technology and test equipment, and able to cover 100 MHz of spectrum. The company thinks it can hit rates beyond 100 Gbits/s.”

 

According to a Cambridge Consultants blog, “Pizzicato uses patent-pending algorithms to achieve the ultra-fast computations – required for the multi-gigabit per second stream – to be performed in real time without degrading the signal.”

 

Conclusion: If you need to get a technology working fast—like for a major trade show—Xilinx All Programmable devices are your best friends.

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There have been many successful Xilinx-based Kickstarter projects but MeshSr’s Zynq-based ONetSwitch Open Source SDN Platform certainly looks to be one of the most innovative yet. It’s based on the Xilinx Zynq Z-7030 SoC, which equips the project with a 1GHz, dual-core ARM Cortex-A9 MPCore processor and 125,000 Kintex-7 logic cells. The Zynq SoC makes an excellent hardware target for SDN developers; you can build a lot from those building blocks. The packed ONetSwitch board also includes four 1Gbps Ethernet ports—very appropriate for an SDN platform.

 

Here’s a block diagram of the ONet Switch board:

 

 

ONetSwitch Block Diagram.jpg

 

 

 

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Xilinx Employee
Xilinx Employee

My daily Google search for “Zynq” turned up this new and incredibly interesting open-source project to develop a Zynq-based driver for the Lime Microsystems LMS7002M second-generation field programmable RF (FPRF) transceiver IC. Myriad-RF was founded by Lime Microsystems, a supplier of flexible transceiver ICs. The project, labeled as being in the incubation stage, is located on the Myriad RF Web site and the project leader is Josh Blum. The Lime Microsystems LMS7002M has a dual-transceiver architecture with on-chip digital signal processing functions that support 2×2 MIMO. The LMS7002M can run any mobile communications and wireless standard including 2G, 3G, and 4G variants and WiFi–licensed and unlicensed. Development is taking place using a Zynq-based Avnet MicroZed board with a Lime Microsystems EVB7 LMS7002M eval board plugged into the MicroZed board’s FMC connector. If you’re into RF design, you’ll want to take a look at this project. However, even if you’re not into RF, you’re going to want to look at this project. Here’s why.

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Xilinx Employee
Xilinx Employee

The OPNFV Project—a community-led, industry-supported, open-source reference platform for Network Functions Virtualization (NFV)—today announced that Enea, Korea Telecom, SK Telecom, Spirent and Xilinx have joined the project to advance the industry's first integrated, open-source NFV platform. NFV is a networking architectural concept that does for networks what virtualization did for servers and other computing hosts: a virtualized network function consists of one or more virtual machines implementing network-related processes and running on top of industry-standard high-volume servers, switches, networked storage systems, or even cloud computing infrastructure. NFV examples include virtualized load balancers, firewalls, intrusion-detection devices, and WAN accelerators. The advantage of NFV is that it exploits programmable hardware to create flexible execution environments that can dynamically serve networking loads and varying applications as needs change without the need to uninstall old hardware and install new.

 

OPNFV (Open Platform for NFV) is working to establish a carrier-grade, integrated, open-source reference platform to advance the evolution of NFV and to ensure consistency, performance, and interoperability among multiple open-source networking components. Because multiple open-source NFV building blocks already exist, OPNFV will work with upstream projects and other standards bodies to coordinate continuous integration and testing while filling existing technological gaps.

 

 

 

 

 

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