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Xcell Daily Blog (Archived) - Page 3

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Xcell Daily Blog (Archived) - Page 3

Xilinx Employee
Xilinx Employee

CASPER (the Collaboration for Astronomy Signal Processing and Electronics Research) is a multi-university collaborative developing hardware and software to streamline and simplify the design of radio-astronomy instrumentation. By providing parameterized, platform-independent "gateware" libraries running on reconfigurable, modular hardware building blocks, CASPER instrumentation platforms abstract away low-level implementation details and allow astronomers to rapidly design and deploy new instruments. One of the designs currently under development is the ADC1X26G ADC board designed to interface a Hittite HMC5913 3.5-bit, 26Gsamples/sec ADC to a Xilinx Virtex-7 XC7VX690T FPGA on a Xilinx VC709 Connectivity Kit and Eval Board using eight of the 80 13.1Gbps GTH SerDes transceiver ports in the Virtex-7 690T FPGA. (See “Test report on 20 Gsps ADC Proof of Concept based on Hittite HMC5913”.)

 

Here’s a block diagram of the CASPER ADC1X26G board design:

 

 

CASPER ADC1X26G ADC board Block Diagram.jpg

 

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Xilinx Employee
Xilinx Employee

Spotted at this week’s DesignCon—a 28Gbps backplane demo using two Xilinx VCU109 Eval boards talking to each other over a big, stubbed-out backplane. The boards are running eight 28Gbps GTY SerDes channels of PRBS31 data over the backplane. Here’s the photo:

 

 

Teraspeed 28Gbps Backplane Demo using UltraScale VCU109 Eval Kit.jpg

 

 

Just look at that big, gorgeous eye on the laptop. That’s what backplane designers want to see.

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Xilinx Employee
Xilinx Employee

At last year’s DesignCon, MoSys demonstrated one of its Bandwidth Engine 2 serially connected, high-speed, 576Mbit 1T (pseudostatic) SRAMs connected to a Xilinx Virtex-7 FPGA using a Xilinx VC707 Eval board modified with a Xilinx Virtex-7 330T FPGA. (See “MoSys Bandwidth Engine 2 (576Mbit 1T SRAM) cozies up to Virtex-7 FPGA using 16 SerDes transceivers running at 14.07Gbps.”) This week at DesignCon, MoSys was showing the same setup but with two Bandwidth Engine 2 devices running in tandem with the Virtex-7 330T FPGA. Here’s a photo of the setup:

 

 

Mosys Bandwidth Engine - 1 Gbit in two Bandwidth Engines connected to a Virtex-7 at 12.5Gbps.jpg

 

 

Many systems—especially high-speed networking systems—need access to big blocks of fast RAM for buffers, queues, lookup tables, and the like. The bigger, the better. There’s never enough memory close enough to the high-speed processing. Shuttling data between processing engines and memory takes time and increases system latency.

 

MoSys’ Bandwidth Engine series is designed to tackle that problem using high-speed SerDes connections to bring the SRAM close to the FPGA. Here’s a closeup of the MoSys Bandwidth Engine 2 board showing the 16 differential-pair traces that connect each Bandwidth Engine 2 to the Xilinx VC707 FPGA board:

 

 

MoSys Bandwidth Engine connected to a Virtex-7 closeup.jpg 

 

You know that memory’s cranking. Just look at that big, copper heatsink!

 

In the same DesignCon booth, MoSys was also showing the demo of a Xilinx 20nm Kintex UltraScale FPGA operating a Bandwidth Engine device, which the company demonstrated last year at OFC 2014. (See: “MoSys Bandwidth Engine 2 and Xilinx Kintex UltraScale FPGA have a 15.625Gbps conversation at OFC.”)

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Xilinx Employee
Xilinx Employee

Napatech has begun shipping its 100Gbps flagship NT100E3-1-PTP, a PCIe Gen3 Ethernet accelerator that assists network appliance manufacturers as they make the jump from 1 to 10 and 10 to 100 Gbps networks. Network analysis at 100Gbps requires 10x the processing—supplied in the NT100E3-1-PTP by a Xilinx Kintex-7 FPGA. The NT100E3-1 delivers more than double the processing performance of its predecessor while maintaining common APIs for fast time to market and staying within the standard PCIe form factor for ease of use with standard server platforms. A hardware abstraction layer allows multiple NT100 PCIe accelerators to work as one unit.

 

 

Napatech NT100 100G PCIe Ethernet Accelerator.jpg

 

 

The NT100E3-1-PTP:

 

  • Employs a CFP4 module for 100Gbps network connection
  • Captures 100Gbps traffic in real time with zero packet loss regardless of frame size
  • Time-stamps every Ethernet frame with 4nsec resolution
  • Accelerates application performance while keeping the server CPU load below 5%
  • Flexibly supports multiple time synchronization schemes including the IEEE1588-2008 Precision Time Protocol (PTP)
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Xilinx Employee
Xilinx Employee

Now that many Xilinx All Programmable devices including most members of the 20nm Virtex UltraScale device family and the Virtex-7 580T and 870T devices can operate quite reliably at transceiver rates in excess of 28Gbps, you’re going to want to know how to design pc boards that support these extreme line rates. Keysight wants to tell you how to do this with a free Webinar on January 22. That’s tomorrow!

 

Register here for “PCB Materials, Simulations, and Measurements for 32 Gb/s.”

 

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Xilinx Employee
Xilinx Employee

If you’re involved in the design of small cells or other sorts of low-power RF applications including telecommunications, wideband tactical radio, and radar, then you’ll be interested in a new White Paper from Cree. The White Paper describes a GaN PA (power amplifier) based on the Doherty architecture that delivers excellent RF power efficiency using an asymmetric structure to permit higher back-off levels while still meeting spectral limit requirements. CFR (crest factor reduction) and DPD (digital pre distortion) algorithms along with DUC (digital up conversion) and DDC (digital down conversion) implemented as IP blocks within the programmable logic of a Xilinx Zynq SoC are responsible for achieving these results from a Doherty PA.

 

 

GaN PA for Small Cells Results.jpg 

 

If you’re interested in a more complete description of these results with hard data, then click here to get a copy of the White Paper “GaN PA Supports 3.5-3.7 GHz Small Cell Applications Using Digital Predistortion” from the IEEE Communications Society and Cree.

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Xilinx Employee
Xilinx Employee

IEEE Communications Society Logo.jpgYou can now access the free, on-demand IEE tutorial “Minimize Development Effort for Complex Wireless Applications Integrating both Hardware and Software on the Zynq All Programmable SoC” on the IEEE Communications Society’s Web site (registration required). Created by Carl Cao, PhD, Wireless System Architect and Yuan Gu, Senior Business Manager at Xilinx, this tutorial provides detailed explanations on topics such as:

 

  • Digital Pre Distortion (DPD)
  • Splitting critical wireless tasks across multiple processor cores and dedicated hardware
  • Implementing multiple radio functions including an entire Digital Front End (DFE) in a Xilinx Zynq SoC
  • Pros and Cons of SMP (symmetric multiprocessing) versus AMP (asymmetric multiprocessing) in wireless designs

 

Using an all-in-one radio DFE (digital front end) as an example, this tutorial demonstrates the abilities of the Xilinx family of Zynq All Programmable SoCs to support complex carrier-grade, high-performance, and low-cost wireless applications.

 

Click here to register and get instant access to the Webinar.

 

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Xilinx Employee
Xilinx Employee

The new Avnet WiLink 8 Adaptor card couples the Texas Instrument WL1835MODCOM8 (2.4 GHz) or WL1837MODCOM8I (5.0 GHz) wireless evaluation boards to the Avnet Zed series of Zynq-based eval cards (ZedBoard, MicroZed, PicoZed, and Mini Module Plus) through two PMOD ports. Documentation and example designs demonstrate the software build process using Yocto and Xilinx’s Open Source Linux Distribution. Details on how to add Wi-Fi, Bluetooth and BLE are covered in detail, helping developers quickly add wireless capabilities for Internet of Things, multimedia, industrial and home automation, security, and M@M industrial applications.

 

 

Avnet WiLink 8 Adaptor Card.jpg

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Xilinx Employee
Xilinx Employee

Last month, National Instruments (NI) introduced the LabVIEW Communications System Design Suite, which combines software defined radio (SDR) hardware with a comprehensive, unified software design flow to help engineers prototype 5G systems. The package includes built-in application frameworks for WiFi and LTE that enable wireless developers to focus on creating specific components based on existing standards rather than designing new algorithms from scratch. It allows people to rapidly combine new communications concepts with real-world I/O. “For some of the academic and industry researchers in our lead user program, this approach has cut the time to a validated prototype in half” said James Kimery, director of RF and Communications at NI.

 

 

NI LabVIEW Communications Design Suite.jpg

 

 

The LabView Communications System Design software is coupled with the company’s USRP software-defined radio development platform for 5G research, which is based on a Xilinx Kintex-7 All Programmable device. (See “Software-defined radio dev platform for 5G research handles MIMO, massive MIMO using Kintex-7 FPGA.”) Wireless engineers can use the NI USRP RIO and the NI LabVIEW Communications System Design software to rapidly prototype real-time wireless communications systems and test them under real-world conditions. You can explore more complex, more capable wireless algorithms and develop systems faster because the LabVIEW graphical system design and programming environment allows you to focus on solving actual wireless communications problems instead of being concerned with underlying implementation details.

 

LabVIEW Communications provides a single, cohesive environment that enables users to program both processors and FPGAs. LabVIEW Communications supports a variety of design languages and approaches including C, .m, and NI’s G dataflow language. The graphical dataflow language is able to span both processor and FPGA execution hardware seamlessly. (For more detailed information, see “Software Synthesis from Dataflow Models for G and LabVIEW.”) LabVIEW Communications also provides built-in tools for data-driven float-to-fixed point conversion to ensure a seamless transition of algorithms designed in G between processor and FPGA hardware.

 

 

 

 

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Xilinx Employee
Xilinx Employee

A big part of the ever-present “go-faster” imperative is getting more bits per second through the same number of pins. Nowhere is that imperative more evident than OpenVPX Gen3 signaling, which Curtis-Wright has realized with its Fabric40 Technology Program to allow its customers to implement 10Gbps and 40Gbps Ethernet (40GbE) or QDR Infiniband communications fabrics over OpenVPX backplanes and cables originally designed for a much lower 6.25Gbps operation. The company’s Fabric40 Program establishes the industry’s first complete end-to-end approach to integrating the latest high-speed fabrics into customer applications. In addition to enabling individual system components with 40Gbps high-speed interconnects, the Fabric40 Program also ensures that all aspects of this new data fabric technology are optimally configured to work together, which greatly reduces our customers’ integration risks and development time. According to Curtis-Wright, the Fabric40 technology delivers 40-100% greater eye height with improved BER and better margin.

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Xilinx Employee
Xilinx Employee

“OK... Here we go… Focus… Speed… I am speed.” – Lightning McQueen, “Cars”

 

Any system design today that’s moving a lot of data between chips, boards, or boxes needs speed—and lots of it—in the form of I/O bandwidth for:

 

  • Serial backplanes
  • Optical interfaces
  • Host and peer communication
  • Chip-to-chip communication

 

That’s the sole topic of a new Xilinx White Paper published today titled “Leveraging UltraScale FPGA Transceivers for High-Speed Serial I/O Connectivity” (WP458) by Brandon Jiao. This 24-page document tells you everything you need to know about high-speed digital communications using Xilinx 20nm UltraScale FPGAs.

 

For example, here’s a handy graphic that shows how many and what type of SerDes transceivers you get with each Virtex UltraScale and Kintex UltraScale family member:

 

 

UltraScale FPGA Transceiver Count.jpg

 

 

Here’s a similar graphic showing you the aggregate I/O bandwidth you get from the GTH and GTY transceivers on each of these devices:

 

 

UltraScale FPGA SerDes Aggregate Bandwidth.jpg

 

 

Finally, here’s a graphic comparing the aggregate device bandwidths available from 7 series and UltraScale Virtex and Kintex FPGAs:

 

 

UltraScale vs 7 series SerDes Aggregate Bandwidth.jpg

 

 

Does your design need 5.6Tbps or just 2Tbps?

 

 

If you’d like much more in-depth information on using these UltraScale SerDes transceivers, then download and read this new White Paper.

 

 

 

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Xilinx Employee
Xilinx Employee

The Interlaken protocol provides chip-to-chip communications in many systems. The faster the communication, the better. Xilinx UltraScale FPGAs incorporate as many as 9 Interlaken integrated hard-core IP blocks to assist you in creating multi-chip systems that scream. The hard Interlaken cores handle data striping and de-striping across lanes, lane decommissioning, channel- and link-level flow control, and two levels of CRC. Each block supports Interlaken communications at a maximum total bandwidth of 150Gbps using 1 to 12 serial lanes operating at 6.25 to 12.5Gbps or 1 to 6 serial lanes operating at 12.5 to 25.78125Gbps. Of course, UltraScale devices have the high-speed serial transceivers needed to support these data rates.

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Xilinx Employee

 

 

4DSP PC820 PCIe Card.jpg

 

 

The PC820 PCIe card from 4DSP harnesses two FMC HPC connectors and an SFP+ optical transceiver socket to a Kintex UltraScale All Programmable device to create a design and implementation platform for applications as diverse as software defined radio (SDR), Radar/Sonar imaging, high-speed communications in data centers, and analog/digital signal processing. The FMC connectors allow you to add a variety of mezzanine cards that might carry ADCs, DACs, RF circuitry, or additional processing resources. 4DSP offers several such FMC mezzanine cards. Here’s a block diagram of the card:

 

 

4DSP PC820 Block Diagram.jpg

 

 

Note: This is the second PCIe card based on a Xilinx Kintex UltraScale card announced and covered in Xcell Daily today. I sense a trend here.

 

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Xilinx Employee
Xilinx Employee

According to this press release appearing on i-Newswire.com, DINI Group has just announced that its DNPCIE_40G_KU_LL PCIe FPGA board based on Xilinx Kintex UltraScale All Programmable devices is now available. (The other DINI Group designation for this board is “Daughter of Godzilla's Bad Hair Day,” in keeping with the company’s unique product naming system.) The board can be populated with a Kintex UltraScale KU070, KU060, KU040, or KU035 device in an 1156-pin, flip-chip BGA package.

 

 

DINI Group DNPCIE_40G_KU_LL.jpg

 

 

The new board also features a QFSP+ optical transceiver socket, two SFP+ optical transceiver sockets, 4Gbytes of on-board DDR4 SDRAM, 144Mbytes of low-latency RLDRAM3, a GPS input for precise time stamping (for high-speed, low-latency packet-processing applications), and “enough debug LEDs to illuminate a small Koi pond.” Here’s a block diagram of the board:

 

DINI Group DNPCIE_40G_KU_LL block diagram.jpg

 

 

 

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Xilinx Employee
Xilinx Employee

NBASE-T Logo.jpgThe NBASE-T Alliance, an industry-wide cooperative effort to promote the development of 2.5 and 5 Gigabit Ethernet over twisted pair copper cabling (2.5GBASE-T and 5GBASE-T) now has 12 new members:

 

  • Aruba Networks
  • Brocade
  • Cavium
  • Centec Networks
  • CME Consulting
  • Intel
  • Microsemi
  • Qualcomm
  • Ruckus Wireless
  • Shenzhen GLGNET Electronics Co., LTD.
  • Tehuti Networks
  • Vitesse Semiconductor

 

Xilinx is already a member of the NBASE-T alliance. For more information about the development of the 2.5 and 5Gbps Ethernet standards, see:

 

NBASE-T aims to boost data center bandwidth and throughput by 5x with existing Cat 5e/6 cable infrastructure

 

 

For additional information about the PHY technology behind NBASE-T, see

 

Boost data center bandwidth by 5x over Cat 5e and 6 cabling. Ask your doctor if Aquantia’s AQrate is right for you

 

 

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Xilinx Employee
Xilinx Employee

If you’re looking at designing a next-generation wireless basestation, you’re looking at developing a lot of new technology including adaptive antenna array (AAA) systems and CRANs (cloud radio access networks). The way data moves and how it is processed in these next-generation basestations will change like never before. Xilinx has published a new 56-page White Paper titled “The Application of FPGAs for Wireless Base-Station Connectivity”(WP450) to help you. Check it out.

 

 

Next-Generation CRAN Basestation.jpg

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Xilinx Employee
Xilinx Employee

You can now prototype and test Xilinx Zynq-based software-defined radio (SDR) systems using the new SDR support tools for MathWorks’ Communications System Toolbox that works with the company’s MATLAB and Simulink. Hardware targets include the Zynq-based Xilinx ZC706 Evaluation Kit and Avnet’s ZedBoard.

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Xilinx Employee

Kevin Morris at EE Journal is a long-time observer of the FPGA world. Today, he published his take on the recent introduction of the new Xilinx SDAccel Development Environment. It’s a long article and you should read it in its entirety, but here are a couple of brief paragraphs from Morris’ article:

 

“If FPGAs are to become the compute engines of the future, the flow of FPGA design must make a tectonic shift toward the software engineer. The devices must seem like processors, and the implementation must feel like programming. Synthesis, simulation, and layout must be replaced by compilation and debug. Detailed control of optimization options must be replaced by rapid iteration and productive workflow. In short, the whole hardware-engineer-centric FPGA process must be turned on its side.

 

“That is exactly what Xilinx is doing today.

 

“Enter SDx (for “Software-Defined (whatever)”), which is Xilinx’s marketing approach to the various flavors of software-based systems engineering. In different application domains, software developers have different dialects. Software-defined networking is markedly different from search, or big data processing, or image and signal processing. So, Xilinx wanted a brand that was extensible to various tribes of software engineers, and which had a basic underlying flow that was understandable and familiar to all flavors of software engineers. The first two examples are SDNet (Software-defined specification environment for networking) and SDAccel (development environment for OpenCL, C, and C++).”

 

If you missed the SDAccel introduction, take a look at “CPU/GPU-like software development environment for OpenCL, C, C++ delivers FPGA-based app acceleration with 25x better performance/W.”

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Xilinx Employee

Spotted at this week’s SC14 (Supercomputing 2014) conference in New Orleans:

 

 

Invea-Tech HANIC-100G Live.jpg

 

 

 

I just had to stop at Netcope Technologies’ booth to find out more. Xcell Daily covered Netcope Technologies’ 100G PCIe card back in May during the Ethernet Technology Summit held in San Jose, CA (see “PCIe Gen3 essential for high-speed FPGA-based Ethernet adapter cards: Netcope Tecnologies”). The card is based on a Xilinx Virtex-7 H580T 3D FPGA. From that previous blog post:

 

“…the Netcope Tecnologies COMBO 100G HANIC accepts one 100Gbps CFP2 optical Ethernet transceiver module and the on-board Virtex-7 H580T 3D FPGA receives the Ethernet streams using four of its GTZ 28.05Gbps SerDes transceivers operating at 25Gbps to communicate with a CFP2 cage. The higher Ethernet data rates require an expansion to a PCIe Gen3 x16 host interface to handle the additional traffic bandwidth.”

 

In July of this year, Netcope Tecnologies in cooperation with CESNET announced successful transfer between an FPGA and host computer memory at a data rate exceeding 100Gbps through two PCIe Gen3 x8 blocks used as a x16 interface using Intel bifurcation technology.

 

Here at SC14 in New Orleans, Netcope Technologies was showing the card’s performance, which pretty much hits the theoretical performance limits, as you can see from this screen shot of the performance dashboard:

 

 

INVEA-TECH Performance Dashboard.jpg 

 

The SC14 demo and the dashboard above prove that the concept works.

 

For more details, see Netcope Technologies’ full report.

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Xilinx Employee
Xilinx Employee

Convey Computer had a lot to say about HLL (high-level language) extensions and FPGA-based application acceleration at SC14 (Supercomputing 14) in New Orleans this week. Convey makes a line of FPGA-based hardware accelerator cards for PCIe computing and server systems including the Wolverine, which is based on a Xilinx Virtex-7 FPGA. Convey is one of several vendors offering COTS (commercial off-the-shelf) accelerator cards that are part of this week’s rollout of the Xilinx SDAccel Development Environment. (See “CPU/GPU-like software development environment for OpenCL, C, C++ delivers FPGA-based app acceleration with 25x better performance/W.”)

 

 

Convey Computer Wolverine FPGA-based Accelerator Card.jpg 

 

Wolverine FPGA-based Application Accelerator for PCIe Systems

 

 

Convey’s booth at SC14 incorporated a very informative poster with a ton of good info about using HLL extensions to accelerate application code using FPGA-based boards. I’m going to quote a significant portion of that poster here, just in case you missed the Convey booth at SC14 or weren’t able to journey to New Orleans this week:

 

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Xilinx Employee
Xilinx Employee

One of the three key components in this week’s Xilinx SDAccel Development Environment announcement at SC14 (Supercomputing 14) in New Orleans is the availability of COTS (commercial off-the-shelf) accelerator cards for HPC (high-performance computing) applications. Alpha Data’s ADM-PCIE-7V3 FPGA accelerator board based on a Xilinx Virtex-7 VX690T FPGA is one of the COTS accelerators directly supported in the initial SDAccel release and this card was on display in action at SC14 in the Xilinx booth. One aisle over in the Alpha Data booth, you could see the company’s next-generation ADM-PCIE-KU3 accelerator card based on a Xilinx Kintex UltraScale FPGA. Here’s a photo of the card from SC14:

 

 

Alpha Data ADM-PCIE-KU3 FPGA Accelerator Board.jpg

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Xilinx Employee

I’ve been writing about the Micron HMC (Hybrid Memory Cube) for a while and today saw one live and in action at the Micron booth here at SC14 (Supercomputing 14). The HMC memory was accepting writes at 21 or 22Gbytes/sec and handling simultaneous reads, also at approximately 21 or 22Gbytes/sec. (It’s amazing how casually we’re treating a Gbyte/sec of unidirectional memory bandwidth—plus or minus—in this video. After all, what’s a Gbyte/sec of memory bandwidth among friends?)

 

In this demo, an Open-Silicon HMC controller instantiated in a Xilinx Virtex UltraScale VU095 FPGA on a Xilinx VCU109 Evaluation Board used sixteen UltraScale SerDes ports to operate one HMC link between the FPGA and the HMC at 15Gbps per line to achieve these stratospheric rates. (There are 16 high-speed serial lines per HMC link and you can use multiple links to connect to an HMC memory for really awesome memory bandwidth.)

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Xilinx Employee
Xilinx Employee

If you’re interested in working with the Micron HMC (Hybrid Memory Cube), then you’ll likely be interested in openHMC—an open-source, AXI4-compliant memory controller for the HMC developed by the Computer Architecture Group at the University of Heidelberg in Germany. It’s a parameterizable IP block that allows you to set different overall data widths, external lane widths, and clock speeds depending on application needs. Micron was exhibiting an HMC board connected to a Xilinx UltraScale FPGA eval board implementing the open-source HMC controller in its booth at SC14 (Supercomputing 14) in New Orleans.

 

 

Open-Source HMC Controller IP for UltraScale.jpg

 

 

The openHMC memory controller implements the following features as described in the HMC specification Rev 1.1:

 

  • Full link-training, sleep mode, and link retraining
  • 16- to 128-byte read and write (posted and non-posted) transactions
  • Posted and non-posted bit-write and atomic requests
  • Read and Write Mode
  • Full packet flow control
  • Packet integrity checks (sequence number, packet length, CRC)
  • Full link retry

 

Currently the following configurations are supported (8 or 16 lanes):

 

  • 2 FLITs per Word / 256-bit datapath
  • 4 FLITs per Word / 512-bit datapath
  • 6 FLITs per Word / 768-bit datapath
  • 8 FLITs per Word / 1024-bit datapath

 

For more information and a free Verilog download of the open-source IP, click here.

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Xilinx Employee

Dini Group SC14 Booth Sign.jpgDini Group has been cranking out several types of boards for HPC (high-performance computing), ASIC emulation, and networking applications using many generations of Xilinx FPGAs. The sign appearing on the right, spotted at the Dini Group’s booth at SC14 (Supercomputing 2014) in New Orleans clearly indicates that yet another board is on the way, based on the latest-generation Xilinx UltraScale architecture. The Web site lists boards based on both Virtex UltraScale and Kintex UltraScale devices.

 

 

 

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Xilinx Employee

This week at SC14 (Supercomputing 14) in New Orleans, Pico Computing unwrapped its Trifecta workstation concept for HPC (high-performance computing). Pico Computing’s Trifecta melds three key HPC technologies—a Xilinx Virtex UltraScale FPGA, Micron’s category-busting HMC (Hybrid Memory Cube), and OpenCL—to create a supercomputing platform with an air-cooled, PC footprint. The heart of the Trifecta platform is this board, which debuted in the Pico Computing and Xilinx booths at SC14:

 

 

Pico Computing UltraScale FPGA HMC Board.jpg

 

 

The large silver square on the left is a Xilinx Virtex UltraScale VU095 FPGA, which started shipping in May, 2014. (See “Xilinx ships first 20nm Virtex UltraScale FPGA – Why this matters to you.”) On the right, you see four smaller silver rectangles; these are the Micron HMC memories. The board has sites for as many as eight HMCs. The HMCs communicate with the Virtex UltraScale FPGA over multiple 15Gbps lanes. HMC memories operate as much as 15x faster while consuming 70% less energy when compared to DDR3 SDRAMs, delivering as much as 240Gbytes/sec of bidirectional bandwidth over high-speed serial links.

 

The third winning technology in Pico Computing’s Trifecta is OpenCL, which allows application developers to exploit the superior performance/watt of FPGA hardware acceleration while continuing to use a familiar software-development environment.

 

According to this week’s press release from Pico Computing, the Trifecta platform will be available in beta version in the first quarter of 2015.

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Xilinx Employee
Xilinx Employee

Earlier this week, Xilinx announced the SDAccel Development Environment for OpenCL, C, and C++, which delivers as much as 25X better performance/Watt to the data center using FPGA-based hardware acceleration. The announcement was timed for the SC14 (Supercomputing 2014) conference in New Orleans where SDAccel is being demonstrated all week in the Xilinx booth. Here’s a short video of Kamran Khan, a Technical Marketing Manager at Xilinx, who captures the basic idea behind SDAccel in less than two minutes:

 

 

 


 

 

 

For more information on the new Xilinx SDAccel Development Environment, see “CPU/GPU-like software development environment for OpenCL, C, C++ delivers FPGA-based app acceleration with 25x better performance/W.

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Xilinx Employee

Last month, Intilop announced availability of a TCP Hardware Accelerator (a TCP Offload Engine or TOE) that could handle 16K concurrent TCP sessions. The Intilop TCP accelerator is available pre-ported and tested on an Alpha Data ADM-PCIE-7V3 card, which I caught in action this week in the Xilinx booth at SC14 (Supercomputing 14) in New Orleans. The Alpha Data ADM-PCIE-7V3 card is based on a Xilinx Virtex-7 VX690T FPGA. Kelly Masood—founder, president, and CTO of Intilop—demonstrated the TOE accelerator for me.

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Xilinx Employee

Today was the first day that the exhibit hall opened at SC14 (Supercomputing 2014) in New Orleans and the Xilinx booth was filled with demos. Xilinx Data Center Architect Shreyas Shah quickly ran me through three of the demos:

 

 

  • FPGA fast Key Value Store
  • FPGA 25G Ethernet Mac
  • FPGA-based NVMe storage controller

 

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Xilinx Employee

25G Ethernet Consortium Logo.jpgThe new Xilinx low-latency 25G Ethernet MAC and PCS IP will be demonstrated in the Xilinx booth at next week’s SC14 (Supercomputing 2014) conference in New Orleans. Bumping Ethernet bandwidth from 10G to 25G improves performance and increases front-panel bandwidth for TOR (top-of-rack) switches and other network equipment by 2.5x, which is no small deal. The Xilinx low-latency 25G Ethernet MAC and PCS IP supports the new 25G Ethernet Consortium spec.

 

 

 

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Xilinx Employee
Xilinx Employee

Three weeks ago, Intilop announced availability of a TCP Hardware Accelerator (a TCP Offload Engine or TOE) that could handle 16K concurrent TCP sessions. The Intilop TCP accelerator is available pre-ported and tested on an Alpha Data ADM-PCIE-7V3 card, which you can see in action next week in the Xilinx booths (#3903 and #4003) at SC14 (Supercomputing 14) in New Orleans. The Alpha Data ADM-PCIE-7V3 card is based on a Xilinx Virtex-7 VX690T FPGA. For more information, see “Intilop’s FPGA-based TCP Hardware Accelerator manages 16K concurrent TCP sessions.”

 

You will also be able to see the following data center and HPC (high-performance computing) demos in the Xilinx booths:

 

  • Key Value Store Acceleration
  • NVMe Flash Storage Platform
  • Low Latency 25G/50G Ethernet MAC
  • Various software-defined development environments

 

 

If you’re at SC14, be sure to stop by the booths of various Xilinx Alliance program members for more interesting demos:

 

  • Alpha Data – Booth #3803: industry-leading FPGA accelerator boards for network processing
  • Auviz Systems – Alpha Data Booth #3803: computer vision and image processing middleware IP
  • Convey Computer – Emerging Technology Booth ET11: Wolverine line of high performance coprocessors
  • The Dini Group – Booth #528: scalable Kintex-7 and Virtex-7 FPGA-based solutions for HPC applications
  • Invea-Tech – Booth #3923: world's first HPC 100GE transmit/receive data stream on xR4 PCIe cards
  • Micron – Booth #1949: HMC interoperability demos on Xilinx Virtex UltraScale devices
  • Nallatech – Booth #1332: high performance computing and network processing
  • Pico Computing – Booth # 3233: HMC operation on Xilinx Virtex UltraScale devices and a software-defined development environment

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