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14-bit, 10Gsamples/sec digitizer employs on-board Kintex UltraScale FPGA for user-defined, real-time processing

by Xilinx Employee ‎01-31-2017 02:00 PM - edited ‎01-31-2017 02:09 PM (14,553 Views)

SP Devices ADQ7_170125_02.jpg 

 

SP Devices’ ADQ7 digitizer boasts one or two 14-bit acquisition channels with an aggregate acquisition rate of 10Gsamples/sec (5G samples/sec in 2-channel mode) with either ac or dc coupling and is available in multiple bus formats including MTCA.4, USB3, PCIe, PXIe, and 10 Gbit Ethernet with a maximum, sustained data-transfer rate of 5Gbytes/sec (over PCIe).

 

Given those specs, you should see an immediate problem: there’s not enough bus bandwidth to get the full, continuous digitized data stream out of the module so you immediately know you’re going to need local storage and on-board processing and data reduction.

 

And what controls that on-board storage and performs that on-board processing (and does practically everything else as well)?

 

 

 

A Xilinx Kintex UltraScale FPGA, of course.

 

 

 

Here’s a block diagram of the dc-coupled ADQ7DC:

 

 

 

 

 

SP Devices ADQ7 Digitizer Block Diagram.jpg

 

 

On the left, you see the two pairs of high-speed ADCs that yield the 10Gsamples/sec acquisition speed. Note that all four of those ADCs directly feed the Kintex UltraScale FPGA, which performs several signal-processing steps including calibration; gain and offset adjustments; triggering; and any user-defined, real-time signal processing. You can define those processing blocks using SP Devices’ Dev Kit or you can order one of the several optional signal-processing modules that SP Devices has already developed for the ADQ7 including:

 

  • Advanced time-domain firmware (–FWATD)
  • Pulse data (–FWPD)
  • Software defined radio (–FWSDR)

 

As you can see from the block diagram, the Kintex UltraScale FPGA also manages the ADQ7 module’s overall timing control and manages the data flow through FIFO queues, into and out of the on-board 4Gbyte DRAM, and over the various interfaces offered in this module family—although the native interface appears to be PCIe. (Note: All Kintex UltraScale FPGA family members have at least one integrated PCIe Gen1/2/3 controller, independent of the on-chip programmable logic.)

 

This digitizer illustrates the use of one Xilinx All Programmable device to implement most of the functions in a complex system. The Kintex UltraScale FPGA in this design implements everything but the ADCs, the clock, the memory, and some of the interface hardware. Everything else is nicely bundled in the one UltraScale device with enough capability left over to allow for the addition of user-defined processing. This sort of flexibility offers real value for system designers.

 

For more information about the ADQ7 digitizer family, contact SP Devices directly.

 

 

 

 

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About the Author
  • Be sure to join the Xilinx LinkedIn group to get an update for every new Xcell Daily post! ******************** Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.