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A Boot Loader for MicroZed. Adam Taylor’s MicroZed Chronicles, Part 6

by Xilinx Employee ‎11-12-2013 02:54 PM - edited ‎05-26-2015 04:34 PM (68,524 Views)

By Adam Taylor

 

When last we looked at the MicroZed board (Figuring out the MicroZed Boot Loader – Adam Taylor’s MicroZed Chronicles, Part 5), we focused upon how the Zynq All Programmable SoC configured both the on-chip processing system (PS) and the on-chip programmable logic (PL) and how this process differs from traditional FPGA configuration procedures. Having now covered the academics behind the configuration of the Zynq SoC in sufficient detail, it is time to look at creating a First Stage Boot Loader (FSBL), which we’ll use together with our software application and programmable logic design to create a configured system that boots after power on or reset.

 

The Xilinx Vivado Design Suite will generate an FSBL that loads your application and configures the Zynq PL. The process is remarkably simple and an example FSBL is provided. First, create a new project using “new -> application project” within the current SDK workspace (the one containing your project) as shown in Figure 1:

 

 

Figure 1 Creating the First Stage Boot Loader Project.jpg

 

Figure 1: Creating the First Stage Boot Loader Project

 

Select whether you will be using C or C++ and also select the board support package (BSP) defined for your system (used_bsp). Then, name the project. In this case I used the name uzed_fsbl.

 

On the next tab, select the Zynq FSBL option from the available templates as shown in Figure 2 and your FSBL project will be created. Now, we are nearly ready to create the boot image. If you have “compile automatically” selected, the FSBL will be complied. Otherwise, it will be complied on demand later on.

 

Figure 2 Creating the FSBL from the template provided.jpg

 

Figure 2: Creating the FSBL from the template provided.

 

But first, we need to make a change to the linker script provided with the FSBL because it has no idea where the DDR memory is located in the processor’s address space. To do this, we need to open the lscrip.ld and specify the DDR memory location in the file. The location of the DDR SDRAM within the address space can be found in the linker script you created for your application. This information can be found in the system.xml file under the hardware platform definition, as shown in Figure 3:

 

Figure 3 Defining the DDR Address Space.jpg 

Figure 3: Defining the DDR address space

 

Figure 3 shows the FSBL lscript.ld with the system’s DDR memory address added in. If you don’t specify the correct DDR SDRAM address, the boot loader will run and the Zynq PL will configure, but the application will not run if it’s configured to execute in DDR memory.

 

Generating a Configuration Image

 

Looking under the Vivado Design Suite’s Project Explorer, you should hopefully now have the following modules:

 

  1. uzed_hw – named after the processing subsystem you created, this is the hardware definition of your file
  2. uzed_bsp   – This is the board support package you created. 
  3. uzed_app  – The application itself.
  4. Used_fsbl  – The first stage boot loader we have just created and modified the linker script for.

 

Each module should have a slightly different symbol identifying its type.

 

 

Because we are creating a bare metal application (no operating system), you need the following files—in this specific order—to create a proper boot image:

 

  1. First Stage Boot Loader (FSBL)
  2. FPGA programming bit file (created in Vivado when we ran the implementation)
  3. C Application

 

Creating a boot image is very simple within the SDK using the “Create Zynq Boot Image” option under the Xilinx Tools Menu as shown in Figure 4:

 

Figure 4 Options for creating the Zynq boot image.jpg

 

Figure 4: Options for creating the Zynq Boot Image

 

Once you have selected the “Create Zynq Boot Image” option, a new dialog box will open as shown in Figure 5, allowing you to select the required files as defined above.

 

 Figure 5 The complete files needed for the boot image.jpg

 

Figure 5: The complete files needed for the boot image

 

It is important to stress that the FPGA programming bit file must always follow the FSBL. Clicking on “create image” will create both a *.bin and a *.mcs file for the target device.

 

The MicroZed board design gives us the option of storing these generated files in either the on-board QSPI Flash memory, which requires a JTAG cable for programming, or within a microSD card plugged into the MicroZed’s microSD card socket. The simpler approach is to use the microSD card. To program the microSD card, insert the SD card into the computer you’re using to generate the boot file and transfer the .bin file to the microSD card. You then need to rename the file on the microSD card to boot.bin.

 

Insert the programmed microSD card into the MicroZed board, make sure the mode pins have been set to configure from the microSD card using the appropriate jumpers, and perform a reset. Your application should then boot.

 

If you wish to configure the on-board QSPI Flash, you’ll need a JTAG cable. You can use the “program flash” option in the SDK or you can use Xilinx iMPACT to program the on-board QSPI Flash.

 

We’ll use the QSPI interface in this example. We specify this option within the Vivado Design Suite as shown in Figure 6:

 

Figure 6 The Vivado view showing the Quad SPI memory.jpg 

 

Figure 6: The Vivado view showing the Quad SPI memory option selected in the Flash memory interfaces

 

The Zynq hardware definition will contain the QSPI IP core and the location of the QSPI memory in the Zynq PS address map. This configuration allows the FSBL to access the QSPI memory and configure the Zynq SoC.

 

The next stage in programming the MicroZed board is to connect it to your PC using the JTAG programming cable. Programming the configuration memory is then as simple as selecting the “Program Flash” option from the Xilinx tools menu within the SDK as shown in Figure 7:

 

Figure 7 Programming the Configuration Memory.jpg

 

Figure 7: Programming the configuration memory

 

Navigate and select the MCS file you generated and enter an offset of 0x0 in the dialog box. Make sure your target hardware is powered on before you click on “program,” as shown in Figure 8:

 

Figure 8 Program Flash dialog Box.jpg

 

Figure 8: The Program Flash dialog

 

Programming the Flash memory may take a few minutes. Verification takes a little longer if you ticked the verify option. Once programming is complete, power down your hardware and the reapply the power. Alternatively, you can just reset the Zynq SoC. Assuming you have the mode pins configured correctly, your MicroZed board will first configure properly; then it will initiate the application; and then your board will spring to life.

 

 

Note: Please see the previous entries in this MicroZed series by Adam Taylor:

 

Figuring out the MicroZed Boot Loader – Adam Taylor’s MicroZed Chronicles, Part 5

 

Running your programs on the MicroZed – Adam Taylor’s MicroZed Chronicles, Part 4

 

Zynq and MicroZed say “Hello World”-- Adam Taylor’s MicroZed Chronicles, Part 3

 

Adam Taylor’s MicroZed Chronicles: Setting the SW Scene

 

Bringing up the Avnet MicroZed with Vivado

Comments
by Explorer
on ‎08-05-2014 01:22 AM

hi Adam,

 

i just follow your instruction, to load a boot file on microSD, but no print on Tera interface ?

 

are we need only one file to run our application ?

by Explorer
on ‎08-05-2014 03:03 AM

hi Adam

 

it's ok, i i succeed to run the boot file on board,i made a mistake with jumper setting, the reason is another tutorial, whitch used another setting of jumper 

 

thank you

by Visitor stefuni
on ‎09-19-2014 07:54 AM

Hi Adam,

 

Followed your instructtions so far, but got an erro creating the FSBL: "Application zynq_fsbl is not supported for the Sw Design".

 

A search turned op this:

http://forums.xilinx.com/t5/Embedded-Development-Tools/Error-creating-FSBL-project-in-SDK-2014-2/td-p/484774

 

Adding the library "xilrsa" (and the required "xilffs") solves the problem

It looks like this is a Vivado 2014.2 specific problem

by Visitor stefuni
on ‎09-19-2014 07:56 AM

Would it be possible to post larger screenshots? Has not been a real problem in the previous parts, but here it would be nice if the text in the screenshots was all readable (memory mapping etc.).

 

Thanks,

 

Stef

by Observer taylo_ap
on ‎09-20-2014 05:50 AM

Hi stefuni 

 

Yes you do need to do that for 2014.2 

 

I will try to dig out the screen shots and send them to Steve for him to add 

 

Adam 

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About the Author
  • Be sure to join the Xilinx LinkedIn group to get an update for every new Xcell Daily post! ******************** Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.