UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AMD, ARM, Huawei, IBM, Mellanox, Qualcomm, and Xilinx collaborate on new Cache Coherent Interconnect for Accelerators (CCIX)

by Xilinx Employee on ‎05-23-2016 08:03 AM (19,743 Views)

 

AMD, ARM, Huawei, IBM, Mellanox, Qualcomm, and Xilinx have joined forces to bring an open, high-performance acceleration framework to data centers. Through the new CCIX Consortium, the companies are collaborating on a specification for the new Cache Coherent Interconnect for Accelerators (CCIX).  For the first time in the industry, a single interconnect technology specification will ensure that processors using different  instruction set architectures (ISA) can coherently share data with accelerators and enable efficient heterogeneous computing—significantly improving compute efficiency for servers running data-center workloads.

 

Power and space constraints within data centers has made application acceleration using methods with superior performance/watt relative to CPUs a high-priority requirement. Applications including big data analytics, search, machine learning, NFV, wireless 4G/5G, in-memory database processing, video analytics, and network processing benefit from acceleration and Xilinx All Programmable devices already deliver this acceleration with superior performance/watt. CCIX will allow application accelerators to access and process data irrespective of where it resides and without the need for continuous CPU/server oversight or complex programming—making acceleration that much more efficient.

 

Simultaneous with the announcement of the CCIX Consortium, Xilinx also announced that CCIX capabilities would be incorporated into acceleration-enhanced versions of the company’s 16nm UltraScale+ All Programmable devices along with HBM DRAM. (See today’s companion blog post: “Xilinx UltraScale+ All Programmable Device Memory Bandwidth Takes Xpress Lane, Jumps 10x with 3D-on-3D HBM.”)

 

Xcell Daily will provide more technical details about these technologies as they emerge.

Labels
About the Author
  • Be sure to join the Xilinx LinkedIn group to get an update for every new Xcell Daily post! ******************** Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.