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Adam Taylor’s MicroZed Chronicles, Part 106: Interrupt Latency Part Two

by Xilinx Employee ‎11-02-2015 10:41 AM - edited ‎01-06-2016 11:04 AM (71,350 Views)

 

By Adam Taylor

 

With the hardware platform defined and built, we can now progress to creating the software that will determine the interrupt latency on the Zynq SoC’s fIRQ and nIRQ interrupts. Both interrupts are stimulated by AXI Timers. Here, the interrupt latency will be the time required to start executing the ISR, not the time to acknowledge the interrupt and start the processing hence it will be a little longer.

 

AXI timers are a very useful component within an embedded system. Each timer instance in a Zynq SoC contains two 32-bit counters, which can be configured in the following modes:

 

  • Generate – The counter counts up or down as selected from a reset value. Once the terminal count is reached, the timer pulses the generate output (if enabled). This mode is used to generate a signal or interrupt at a predefined time interval.
  • Capture – Assertion of the timer’s external Capture Trigger signal stores the value of the counter when the trigger signal is asserted. This mode can be used to measure the duration of external events.
  • PWM – Uses both of the timer’s counters to create a PWM signal. Timer 0 defines the overall period and timer 1 defines the period’s high time.

 

Image1.jpg

 

 

 

We will be using both of of the Zynq SoC’s timers in the generate mode (default count up and auto reload mode). To ensure we do not have timing issues caused by interrupts occurring at precisely the same time, both timers will be set for different intervals.

 

In generate mode, we can determine the interval using the equation below:

 

 

Interval = (2^32-1 – Counter Reset Value + 2) * Clk Period

 

 

With a clock frequency of 100MHz and using counter reset values of 0xF000 0000 and 0xF8035280, the timers will generate interrupts at 2.684 seconds on nIRQ and 1.339 seconds on fIRQ.

 

With the timers configured, my first plan as I mentioned last week was to use EMIO GPIO to drive the freeze pin on the AXI Timer and freeze the timer value. To do this the ISR would first assert the freeze pin. It would then calculate the time taken between the timer generating the interrupt and the freeze pin being asserted.

 

Running the code on the ZedBoard I achieved the following results for the fIRQ and nIRQ stopping the interrupt using the freeze pin:

 

Image2.jpg

 

These results indicate an interrupt latency of approximately 700nsec for both interrupts. However, asserting the EMIO GPIO signal takes a number of cycles, which significantly alters the result. I therefore decided to modify the code slightly.

 

Instead of driving the freeze pin, I decided instead to read the value on the AXI Timer as soon as the ISR is called. This change alters the results by reducing of the interrupt latency by nearly 150nsec, as shown below:

 

 

Image3.jpg

 

 

 

To demonstrate the impact other system configurations and parameters can have upon the interrupt latency, I decided to disable the processor caches and rerun both tests. This considerably increases the measured latency time for both approaches, as would be expected:

 

 

Image4.jpg

 

Using the Freeze Input with Caches disabled

 

 

 

Image5.jpg

 

Reading the AXI timer with Caches disabled

 

 

 

I have uploaded the code to GitHub.

 

Next week, we will look at how we can combine this with the XADC to receive an external analog signal.

 

Incidentally I will be at the Embedded Systems Conference in Minneapolis this week (4-5th November) please come say hello if you are attending.

 

 

If you want E book or hardback versions of previous MicroZed chronicle blogs, you can get them below.

 

 

 

  • First Year E Book here
  • First Year Hardback here.

 

 

 MicroZed Chronicles hardcopy.jpg

 

 

  • Second Year E Book here
  • Second Year Hardback here

 

 

MicroZed Chronicles Second Year.jpg 

 

 

 

You also can find links to all the previous MicroZed Chronicles blogs on my own Web site, here.

 

 

 

Comments
by Visitor joe4702
on ‎11-03-2015 07:21 AM

For the test with caches disabled, I assume you meant to say "considerably increases the measured latency time...".

Latency is 6.2 and 3.6 uSec with caches disabled vs. 720 and 530ns with caches enabled.

by Observer taylo_ap
on ‎11-11-2015 01:23 PM

Hi Joe 

 

Yes you are correct apologies for  that I will ask for it to be corrected 

 

Thanks for reading 

 

Adam 

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About the Author
  • Be sure to join the Xilinx LinkedIn group to get an update for every new Xcell Daily post! ******************** Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.