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Adam Taylor’s MicroZed Chronicles, Part 110: SDSoC Coherency and FFT size

by Xilinx Employee ‎11-30-2015 10:51 AM - edited ‎01-06-2016 10:47 AM (13,286 Views)

 

By Adam Taylor

 

As we begin to use the Zynq SoC’s XADC, I first want to discuss two topics: FFT sizing and coherent sampling when sampling sine waves. Understanding these concepts is important to obtaining the most accurate information when we examine the frequency spectrum. They will allow us to examine the effects of our signal processing algorithms, best examined within the frequency domain.

 

Of course the XADC samples within the time domain so we must employ post processing to convert this time-domain information into the frequency domain. A Fast Fourier Transform is the most common method for accomplishing this task (see Xcell issue 91).

 

The theoretical noise floor for an ADC is given by the equation:

 

 

Image1.jpg 

 

Where n is the number of bits of the ADC.

 

The FFT noise floor is determined by a similar equation, with an additional parameter to allow for theft processing gain:

 

 Image2.jpg

 

 

The Zynq SoC’s XADC has 12-bit resolution and I am going to use an FFT size of 1024, which results in a noise floor of -101 dB.

 

With the FFT size determined, we need to ensure that we sample correctly using this FFT Size. At the most basic level, this is the difference between coherent and non-coherent sampling. If we sample coherently, there are an integer number of sinewaves within the data-capture window (which is also the FFT Size). For example if we wish to store 1024 samples we should ensure there are an integer number of cycles contained within that sample buffer.

 

Failure to ensure that there’s an integer number of samples in the sample window results in spectral leakage in the frequency domain due to discontinuities and these discontinuities impact the resultant frequency spectrum.

 

We can use the relationship below to ensure that we have an integer number of cycles:

 

 

Image3.jpg

 

 

 

Where Fin is the sampled input signal frequency and Fs is the sample rate.

 

We can rearrange this equation to correctly select an Fin that results in an integer number of cycles for the sample size and number of samples required:

 

 

Image4.jpg

 

 

 

It is best to use a prime number of cycles to prevent repetitive patterns and to ensure a random quantization of the noise floor.

 

The XADC has an Fs of 961538Hz, so if we want seven integer cycles and have a 1024-sample buffer, we require an input frequency of 6573.017Hz. Plotting this in Microsoft Excel, we see the following in the time and frequency domains. (Note: I have used Excel to generate all example data here not hardware.)

 

 

Image5.jpg

 

Seven Complete Cycles within the 1024-sample buffer

 

 

 

Image6.jpg

 

Coherent FFT only spectral content is within the bin of Fin only (6573.017 Hz)

 

 

Modifying the model to provide a non-coherent sample, we see the effects on the time domain and frequency domain below:

 

 

Image7.jpg

 

3.123 Cycles within the 1024-sample buffer

 

 

 

Image8.jpg

 

FFT of incomplete cycles showing smearing around the fundamental

 

 

We can use post processing and a Hanning window on a non-coherent sample to correct for spectral leakage. However, it is better to correctly consider the elements first.

 

Now we understand how to get the best performance by correctly configuring input signal and output post processing.

 

 

If you want E book or hardback versions of previous MicroZed chronicle blogs, you can get them below.

 

 

 

  • First Year E Book here
  • First Year Hardback here.

 

 

 MicroZed Chronicles hardcopy.jpg

 

 

  • Second Year E Book here
  • Second Year Hardback here

 

 

 MicroZed Chronicles Second Year.jpg

 

 

 

You also can find links to all the previous MicroZed Chronicles blogs on my own Web site, here.

 

 

 

 

 

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About the Author
  • Be sure to join the Xilinx LinkedIn group to get an update for every new Xcell Daily post! ******************** Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.