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Adam Taylor’s MicroZed Chronicles, Part 111: SDSoC and a Finite Impulse Response Filter PS implementation

by Xilinx Employee ‎12-07-2015 09:50 AM - edited ‎01-06-2016 10:40 AM (22,499 Views)

 

By Adam Taylor

 

Modern embedded systems attempt to shorten the analog signal chain using wide-bandwidth ADC’s and DAC’s at high sample rates. This design technique allows you to use DSP techniques to process the signal. Using these techniques avoids or diminishes analog-design aspects including drift, tolerances, aging, and temperature effects. Of course using DSP techniques present their own challenges.

 

Over the next few blogs we are going to look at how we can create a low-pass FIR (Finite Impulse Response) filter to filter the signal received from the Zynq SoC’s XADC. Initially, we will use the software-driven PS (Processor System) side of the Zynq SoC to execute the filter. Then we will accelerate FIR filter execution using the Zynq SoC’s PL.

 

First we must design the FIR filter. We can us a mathematics package like MathWorks’ Matlab, GNU Octave, or even Microsoft Excel. There is a good explanation of FIR filters and how we can design them within issue 78 of the Xcell Journal.

 

For this example I am going to use GNU Octave to generate the filter kernel coefficients. If you wish to follow along and use Octave at home, you will need to install Octave’s control and signal packages which are available from the octave-forge.

 

For this example, we are going to set the FIR filter’s stop band at 100 KHz. From the previous blog post in this series, the XADC sample rate (Fs) is 961.538KHz. That gives us a Nyquist frequency of 480.769 KHz. We generate the coefficients required for this filter using Octave and the signal package. FIR filters are symmetrical se we need an odd number of coefficients. We will use 11 coefficients for this filter. You can see how these have been generated below in Octave:

 

 

Image1.jpg

 

 

We also use Octave to plot the resulting filter’s frequency response of the filter (below). The plot shows us the stop band and the roll off. We can make the filter roll off sharper by using more coefficients in the filter kernel.

 

 

Image2.jpg

 

 

Now that we have designed the filter using Octave, it’s time to develop the C application that we will be running. Building upon the previous XADC example, we will sample the XADC a number of times. When the defined number of samples have been captured, the filter algorithm will be run across the entire sample buffer.

 

The FIR filter code has been designed to enable acceleration within the PL and appears below:

 

 

Image3.jpg

 

 

I generated the SD Card image for this system and then used the Digilent Analog Discovery Module to stimulate the design at two frequencies: one within the passband at 13 KHz and one within the stopband at 200 KHz.

 

The first thing I did was to capture the raw input to the Filter and examined the signals within both the frequency and time domain as you can see below:

 

 

Image4.jpg

 

Pre Filter Input – Both Frequency and time Domain

 

 

The second thing I did was to capture the output of the filter and compare the filtered result against the input signal in the frequency domain:

 

 

Image5.jpg

 

Filter IP signal top and filter OP signal bottom, Fin = 13KHz

 

 

The final step was to subject the filter to a signal outside the passband and check that the filter attenuates out-of-band signals correctly. For this I applied a 200KHz signal as shown below. You can see the XADC output prior to the filter and the filter output, with the 200KHz signal significantly attenuated:

 

 

Image6.jpg

 

Stopband Filter IP Fin = 200 KHz

 

 

Image7.jpg

 

 Stopband Filter OP Fin = 200 KHz

 

 

With the filter implemented, all that remains is to determine the number of clock cycles that is taken to run the FIR filter algorithm on the sample buffer. For the example running on the Zynq SoC’s PS side, the number of clock cycles taken to implement the filter was 537946:

 

Image8.jpg

 

 

We will look next at how we can accelerate the FIR filter’s performance using the Zynq SoC’s PL side.

 

Note: We could use the XADC streaming output and place an AXI filter in the hardware definition. That would offer the best performance. However, this would not enable us to demonstrate how we can first implement a FIR filter in C and then accelerate it using SDSoC.

 

 

 

If you want E book or hardback versions of previous MicroZed chronicle blogs, you can get them below.

 

 

 

  • First Year E Book here
  • First Year Hardback here.

 

 

 MicroZed Chronicles hardcopy.jpg

 

 

 

  • Second Year E Book here
  • Second Year Hardback here

 

 

 MicroZed Chronicles Second Year.jpg

 

 

You also can find links to all the previous MicroZed Chronicles blogs on my own Web site, here.

 

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About the Author
  • Be sure to join the Xilinx LinkedIn group to get an update for every new Xcell Daily post! ******************** Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.