We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Adam Taylor’s MicroZed Chronicles, Part 116: Test Pattern Generation

by Xilinx Employee on ‎01-25-2016 05:46 PM (919,999 Views)


By Adam Taylor


I now want to explore how the VDMA module works in detail. The first step I am going to take is to create a simple application that generates a video test pattern output using the ZedBoard’s VGA port. This approach simplifies the environment (versus the complete Embedded Vision Kit configuration) so that we can more easily explore the VDMA IP block.


I am going to focus on creating the test pattern and displaying it on a screen this week. This initial build will not use the Zynq SoC’s PS (Processor System). Instead, I’m implementing the test-pattern generator within the Zynq PL (Programmable Logic).


The first thing to do is add in the required IP modules from the IP Library. We will need:

  • Test Pattern Generator configured for 800x600 pixels, configured for one pixel per clock and tartan colour bars.
  • Video Timing Generator – configured for 800x600 pixels at 60 Hz, outputting RGB and one pixel per clock.
  • AXI4-to-video-out – configured as the slave.
  • Clock Wizard configured to generate 100MHz 40MHz clocks.


With the blocks configured as described above, the first thing to do is to simulate the test-pattern generator and see that it functions as required. We can stimulate the clock inputs using the simulation clock generator. The image below shows the configuration I used for simulation.





The Vivado simulator produced the waveform below. Note that we need to ensure that we simulate a number of frames because it takes a number of frames for the AXI4-to-video-out stream to synchronise and lock. Before it locks, it will not output any VGA sync pulses or pixel values. We therefore need to ensure the configuration is one that allows it to synch up and lock.





Once we are happy with the simulation performance, we can take the next step and build the hardware. Before we implement the hardware, we need to break out the Horizontal and Vertical syncs to the ZedBoard 15-pin VGA connector. We also need to address the VGA spec of 24 bits/pixel, consisting of eight red, green, and blue bits per pixel. The ZedBoard only supports 4 bits of pixel information for red, green, and blue channels and combines these bits with simple resistor networks to generate the required analog voltages.


I used the slice function below to split the AXI4-Stream-to-Video-Out IP Block’s 24-bit pixel output into the correct values for the ZedBoard. It is then a simple case of adding the correct XDC file with the locations required.






I ran the above design through Vivado twice: once with the test-pattern generator first outputting the tartan bars test pattern and then the simpler color bars, which can be seen below.









Now we know that we can generate the test pattern successfully. In our next blog, we will add in the Zynq PS, which will give us the ability to change the test pattern generator on the fly and also to insert the VDMA block into the flow and move the test-pattern information to memory so the Zynq PS can access the information for further processing. But at least now we know that the base functionality is present.



If you want E book or hardback versions of previous MicroZed chronicle blogs, you can get them below.




  • First Year E Book here
  • First Year Hardback here.




 MicroZed Chronicles hardcopy.jpg



  • Second Year E Book here
  • Second Year Hardback here



 MicroZed Chronicles Second Year.jpg




You also can find links to all the previous MicroZed Chronicles blogs on my own Web site, here.








by Adventurer
on ‎02-01-2016 01:54 AM



Could you share source files ?
I can't reproduce your example design (Vivado 2015.2).
AXI-Stream to Video Out core can't lock incoming stream and just set vtg_ce to low.

by Xilinx Employee
on ‎02-01-2016 02:26 PM

Toshas, the code for all MicroZed Chronicles blogs is available on Github.




by Visitor isaacverdu
on ‎02-08-2016 01:08 AM



Which version of Vivado is this? I'm running 2015.4 and can't use the Test Pattern Generator module, says it's locked due to licensing restrictions (I'm running the System Edition). Weird thing is, I have an older project (2013.3) which does allow me to use the IP with the same license. Am I missing something here, or did Xilinx just changed the licensing scheme for this module?


Best regards



by Observer taylo_ap
on ‎02-08-2016 11:54 AM



Please check you have the AXIS to video out set as the master, and that you have set up the Video timing generator and the test pattern generator for the same parameters.


let me kow if you are stll struggling and I will dig out the project, or recreate it for you 



by Observer taylo_ap
on ‎02-08-2016 11:58 AM



I am not sure about the licencing for this module, looking onlien though I think you need the core license which appears pretty easy to obtain from the link here http://www.xilinx.com/products/intellectual-property/tpg.html


let me know if I can help more 



by Adventurer
on ‎02-09-2016 12:30 AM

Hi, taylo_ap!


Problem solved!

It was in value of constant_1 (fid input of axi-video out).

"0" or unconnected works fine.

by Visitor isaacverdu
on ‎02-09-2016 02:02 AM

Thanks Adam.

by Visitor jk163393
on ‎04-13-2016 02:54 AM

hello I used your model to generate an output signal with a generator test
No results because my IP VTG has a Axi entree while your a clock
How do I fit? or how can I use this Axi? Should I add another IP or not?
Thank you for telling me

by Observer taylo_ap
on ‎04-13-2016 09:25 AM

jk163393 (Newbie)


This is a really good point I upgraded to Vivado 2015.4 after this blog (which I suspect you are using?) this has a new TPG which has an AXI port on it check out the link below which shows how I adapted this and what is needed. 


What is needed is to mapp in the TPG in your SW application and configure it from the PS 


Let me know if you need anything else





by Visitor jk163393
on ‎04-14-2016 01:10 AM

Hello Adam
Thank you for your reply
Except that this time I do not think saving data
I just wish the display on an HDMI output but I'll try to follow this model
I use the 2015.3 version of Vivado
And to solve my problem I thought using the AXI BFM Cores block that controls connectivity Master / slave with IP creates
But I still have a problem License and no track for download.

thank you to react

by Visitor jk163393
on ‎04-18-2016 12:32 AM

Hello Adam
The VTPG you use in Vivado 2015.4 requires that it be controlled by the Zynq
What I mean this is a simple test for release on Video out.
Otherwise if you have a simple model for Vin, Vout and hybrid does not hesitate to tell me
Thank you

by Observer taylo_ap
on ‎04-18-2016 12:15 PM

Yes it is now configured over the AXI interface you can get it up and running with the code below, assuming you have configured it one would a normal peripheral 


status = XV_tpg_IsReady(&ptpg);
printf("Status %u \n\r", (unsigned int) status);
status = XV_tpg_IsIdle(&ptpg);
printf("Status %u \n\r", (unsigned int) status);
XV_tpg_Set_height(&ptpg, (u32)600);
XV_tpg_Set_width(&ptpg, (u32)800);
height = XV_tpg_Get_height(&ptpg);
width = XV_tpg_Get_width(&ptpg);
XV_tpg_Set_maskId(&ptpg, 0x0);
XV_tpg_Set_motionSpeed(&ptpg, 0x4);
printf("info from tpg %u %u \n\r", (unsigned int)height, (unsigned int)width);
XV_tpg_Set_bckgndId(&ptpg, XTPG_BKGND_COLOR_BARS);
status = XV_tpg_Get_bckgndId(&ptpg);
printf("Status %x \n\r", (unsigned int) status);
status = XV_tpg_IsIdle(&ptpg);
printf("Status %u \n\r", (unsigned int) status);

by Newbie jjahlers
on ‎04-18-2016 03:42 PM

"I used the slice function below to split the AXI4-Stream-to-Video-Out IP Block’s 24-bit pixel output into the correct values for the ZedBoard."


Can you provide details on the Slicer?  Which 4 bits did you use?

by Observer taylo_ap
on ‎04-19-2016 01:40 PM



According to my log book


Red is bits 7 -  0

Green is bits 8 - 15

Blue is bits 23 -16


I used the least significant 3 from each of them e.g. 3-0, 19-16 and 11 -8



by Newbie jjahlers
on ‎04-19-2016 03:19 PM

Thanks for the quick reply to the bits you used. Have you tried configuring the TPG to display a SOLID Background color.  I have a design that uses the 4 MSB to get from 8 down to 4 and I'm having an issue that the SOLID Background doesn't display but Color Bars do!?!

by Observer taylo_ap
on ‎04-20-2016 12:35 AM



That is a very odd issue, I have run simulation and the zedboard with both the colour bars, tartan pattern and the solid background. I did not put any images up of the solif background as it does not look so exciting.


A few questions from me

1) What version of TPG are you using

2) Have you simulated the colour bars and the solid pattern

3) Have you probed the output Vsync and HSync timing are correctly timed

4) Does the AXIS to Video lcoked signal get asserted 


You may want to consider adding a ILA to check on these in the actual design - the next issue of the blog which you can find here shows you hwo to do this https://forums.xilinx.com/t5/Xcell-Daily-Blog/Adam-Taylor-s-MicroZed-Chronicles-Part-117-Hardware-in-the-loop/ba-p/679216

by Participant bilalqureshi
on ‎04-20-2016 01:41 PM

I am wondering how could I get the source code for the test generator ? I am also interested to know about the configuration of Video Timing Generator and AXI4-to-video-out.


This is really interesting blog and I would like to imnplement on the ZedBoard using Vivado 2015.4. Any help would be appreciated in advance.  

by Newbie jjahlers
on ‎04-20-2016 03:25 PM

Here is the answers to your questions:


1) v7.0

2) No

3) Probed the vsync to make sure that it was 60 Hz

4) Yes


I'm actually the verifier of the person who made the design but we do plan to debug this in lab.  I was just trying to confirm the TPG solid colors work and it sounds as though they do.  The color bars displayed in your image are different from ours.

left to right looks like this on mine:
white, yellow, teal green, pink, red, blue, black
grey, pink, yellow, red, teal, blue , green black
by Participant bilalqureshi
on ‎04-21-2016 06:17 AM

I am facing the licence problem for the IP "Video Test Pattern Generator" in Vivado 2015.4. 

by Observer taylo_ap
on ‎04-21-2016 11:12 AM



The source code for the test pattern generator is proivded above in answer to another comment.


The settings for the timing control and the axis to video out are defined above in the blog there is not too much to it though you may find the blogs 





Interesting as they use the V 2015.4 TPG


I am afraid I am not sure what licensing issue you refer to 

by Observer taylo_ap
on ‎04-21-2016 11:14 AM



I think mine starts white it is just my monitor is a little dusty.... I shall clean it now Smiley Happy 


Hope it wors OK for you in the lab 

by Adventurer
on ‎04-25-2016 02:13 PM

Kindly mention the file name of the source code for part 116. 


In the following link there are many files and I could not see part 116 "file name". Secondly, I am not sure whether it's free to download the source code or not. 




by Observer taylo_ap
on ‎04-25-2016 11:33 PM



Hello, there is no source code for this one required you just need to connect the blocks as shown (in the right version of vivado) 


All of the software is free to download from the github 



by Adventurer
on ‎04-29-2016 04:47 AM


Anyone can please share the HDL file of TPG ? In Vivado 2015.4, the TPG appear as pre-production which is locked and cannot be configured. 


Video Test Pattern Generator.png

Test Pattern Generator_lock.png



by Observer taylo_ap
on ‎04-29-2016 09:18 AM



You need to get the license from here http://www.xilinx.com/products/intellectual-property/tpg.html click on the get license 


If you look at the red warning at the bottom of the IP box it informs you, you need to license it.


If you want to configure it then over the AXI link I have posted the code above



by Visitor jk163393
on ‎05-02-2016 07:49 AM

Hi Adam,

tell me please which version you are using you?

Thanks you

by Observer taylo_ap
on ‎05-02-2016 10:33 AM



This version was done in Vivado 2015.2 I think as it correlates with SDSoC version at the time, it will be different if you use 2015.4 as the TPG is changed to require software. 



by Visitor jk163393
on ‎05-04-2016 01:07 AM

Hi Adam,

Could I know how you create your IP VGA and possibly your party SDK? The constraints I can file fend me

I can switch to an HDMI output but the sdk part will be helpful given that I am also on the Zedboar

by Adventurer
on ‎05-04-2016 02:23 PM

I have tested VGA signals v_sync and h_sync generated at the rate 60 Hz by connecting them to LEDs on board, which works fine on ZedBoard but there is no output on the screen just the screen turns black. The frame size is 640 x 480 pixel.  

I am not sure about the frame rate of DELL screen which I have. Any idea how to detect the frame rate of a screen ? I guess I need to synchronize the VGA signal from Zedboard according to the DELL screen. Any idea how to do this ?

by Adventurer
on ‎05-05-2016 08:18 AM



The VGA signals h_sync and v_sync are TTL signals, while red, green, and blue are are 0.7V peak-to-peak (0V for black level, 0.7V for full color intensity).


I am not sure how to set the voltage levels on VGA connector of the Zedboard. I just implment the design on the Zedboard and I read 3.3 V on the scope at the following pins. 


Pin 1:  Red

Pin 2:  Green

Pin 3:  Blue

Pin 13: h_sync

Pin 14: v_sync


In the XDC file, the clk is connected to 100 MHz which is divided by 4 to get 25 MHz to get 60 frames of size 480 x 640 pixels per second. Could you please help me to set the IOSTANDARD (LVCMOS18, LVCMOS25, LVCMOS33) in teh XDC file for the VGA signals ?  



by Observer taylo_ap
on ‎05-05-2016 11:52 AM



The frame rate of the monitor is determined by the VGA signals it receives, otherwise how else could the monitor detect and work at different resolutions.


have you checked that the monitor can work with the settings you have ? Have you checked the Syncs are the right plolarity for the frame rate desired?



by Observer taylo_ap
on ‎05-05-2016 11:55 AM



There is nothing to set in the FPGA IO standards, the FPGA outputs digital signals. If you look at the zedboard design (schematics) you will see a simple resistor DAC that will generate the required analogue voltages it is quite popular for simple VGA applicaitons 



by Adventurer
on ‎08-11-2016 11:48 AM

So maybe the AXI4-Stream to Video Out IP in my Vivado 2015.4 is old and buggy, but it does not do blanking.  In VGA, when you're not sending actual pixels you're supposed to send black.  But apparently this core doesn't do that so it wouldn't be suited for VGA (at least the way I connected it, with the s_axis_video_tdata input fixed to "orange" rather than the pattern generator because I wasn't sure how to control said generator).


To get this working, I had to multiplex the vid_data output of the AXI4-Stream to Video Out so that when vid_active_video is 0 it sends zeros rather than that output.  (Funnily, there's no multiplexer IP in Vivado 2015.4; took me a while until I figured out how to use an Adder/Subtracter for this.)


Has this been fixed in newer versions, is your monitor special, or is it my fault for overriding the pixel data input with a constant value?

by Observer taylo_ap
on ‎08-12-2016 02:25 AM


This is a good question, Vivado 2015.4 uses AXIS to Video Version 4.0 which accepts blanking signals in and also gives blanking signals out which you can use for the blanking. 


The AXIS stream from the TPG does not take into account blanking periods as it does not need to hence we need to make sure the FIFO size is sufficient in the AXIS to Video Out.


With regard to blanking you are correct you do need to blank, I think my new LCD monitor is capable of handling it OK without blanking period unlike older CRT monitors.


Thanks for reading



by Adventurer
on ‎11-17-2016 09:30 AM

I just found about Digilent's rgb2vga IP.  This is a very simple IP that takes a vid_io input (such as the one generated by the AXI4-Stream to Video Out IP) and generates the red, green, and blue outputs (by default with 5-6-5 bits respectively, but parameterizable to 4-4-4 for the MicroZed and Zedboard).  Additionally, it performs the blanking I commented earlier.


This IP is part of Digilent's ZYBO reference designs, which can be downloaded from https://github.com/Digilent/ZYBO.  The rgb2vga IP is located in Projects/hdmi_in/repo/digilent/ip/rgb2vga_v1_0 (part of the HDMI In project).  Similarly, there's an rgb2dvi IP in the HDMI Out project which allows driving the HDMI output of the Zybo directly (but not of the Zedboard, as its HDMI port is controlled by an ADV7511 IC).


Maybe it's not a good idea to use this IP in an example/tutorial like this as it hides what's really going on, but I recommend it for designs as it saves the user from adding all the xlslice blocks (and the blanking ones).

by Newbie ranjithanih@gmail.com
on ‎11-06-2017 11:05 PM



I’m implementing the test-pattern generator with the Kintex 7 evalution board (vivado 17.2)), which modules it's required, if possible anyone send the block diagram for this.

by Xilinx Employee
on ‎11-07-2017 10:50 AM



You can connect directly with Adam at http://adiuvoengineering.com.




About the Author
  • Be sure to join the Xilinx LinkedIn group to get an update for every new Xcell Daily post! ******************** Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.