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Adam Taylor’s MicroZed Chronicles, Part 117: Hardware in the loop debugging with SDK and the In-Chip Logic Analyzer

by Xilinx Employee ‎02-01-2016 02:31 PM - edited ‎02-01-2016 02:34 PM (16,044 Views)

 

By Adam Taylor

 

I was hoping this week to focus on how to use the VDMA, however a few things happened as I worked towards this and these things demand a blog in their own right. My end goal is to create an imaging system using the ZedBoard Embedded Vision Kit using SDSoC. This means that the hardware platform built in Vivado has to be in an SDSoC compatible version.

 

Until recently I was using SDSoC V2015.2.1, having upgraded in the last week to Vivado and SDSoC 2015.4. This upgrade brought about several IP upgrades that required some changes to the previously developed software. As a result, I did not see what I expected on the VGA monitor when I first built the system using the upgraded tools and IP.

 

The biggest change was the new system uses software to configure the test pattern generator, which makes it more complicated to simulate. I know we can use Bus Function Models to simulate the Zynq interface. However, I wanted to troubleshoot both my software and hardware at the same time (because I only have one day a week to write theses blogs and, to get it working, I typically write a blog on a Sunday). Therefore, the best way to troubleshoot is to have the actual hardware in the loop during the test so that I can run my software on real hardware.

 

We can do this very simply within the Vivado environment by making use of the In-chip Logic Analyzer (ILA) IP block, which can be attached to either signals and buses or to internal AXI interfaces. Once these analyzers have been inserted, we can not only monitor them within Vivado but we can also use SDK to download our software application and run that too. Therefore, we can use the ILA and the ability to debug (breakpoints, watching memory etc.) the software to find the root cause of our problem.

The ILA block is available from the Vivado IP catalog and we add it to our design like we would any other IP module. We have the option of monitoring AXI interfaces (and which type of AXI4—Lite, streaming, etc.) or simpler bits and buses. We configure these choices by double clicking on the block and customizing as required.

 

To help me debug the test pattern design, I added three ILA blocks to monitor the outputs of the Video Timing Generator and the AXI-Stream-to-Video outputs. I also added an ILA to monitor the AXI stream generated by the test pattern generator as shown below:

 

 

Image1.jpg

 

AXI Stream monitoring ILA

 

 

 

Image2.jpg

 

Timing Generator and Video Output ILA

 

 

After I inserted the required ILA’s into the design, I re-generated the output products for the new design implemented and generated the bit files. I then opened the hardware manager in Vivado and also opened SDK. We need both going forward.

 

Within the Vivado Hardware manager I programmed the ZedBoard’s Zynq over the JTAG cable, along with the bit file. The hardware manager also identifies and loads an LTX file that contains information about the signals being monitored by each ILA. Within the hardware manager, you will see an ILA window for each ILA in your design. These windows enable you to set triggers and analyze the results.

 

 

Image3.jpg

 

ILA window open and triggered before the SW application was executed

 

 

However, it will do nothing until we run some software. In this case, this we can do so very simply with the SDK. We need to create a new debug configuration over GDB that only downloads the application and not the FPGA configuration file as shown below:

 

Image4.jpg 

 

Creating the Debug Application

 

 

Once that is complete, we can launch the debugger and run the software as we desire on the Zynq SoC. We can add breakpoints and pause execution as required to investigate any issues we see.

 

 

Image5.jpg

 

 

 

At the same time, Vivado’s hardware manager allows us to configure the ILA’s so that they trigger when software-generated events occur. That way, we can check whether or not they do occur. Depending upon what we have connected to the ILA, we can also monitor events that are asynchronous to the software.

 

 

Image6.jpg

 

Setting the trigger on the AXI Stream monitor

 

 

Image7.jpg

 

 

Triggering on the AXI Stream following the issue of the software run command with the application executing on the Zynq SoC

 

 

 

Following this approach enabled me to quickly identify that the issue was the AXI-Stream-to-Video-Output IP was not correctly locking. That was the cause of the problem.

 

This approach also enabled me to see that the test pattern generator was correctly generating its output under software command.

 

Sorry for the diversion but I think it was a rather useful distraction.

 

 

 

The code is available on Github as always.

 

If you want E book or hardback versions of previous MicroZed chronicle blogs, you can get them below.

 

 

 

  • First Year E Book here
  • First Year Hardback here.

 

 

 

 MicroZed Chronicles hardcopy.jpg

 

 

  • Second Year E Book here
  • Second Year Hardback here

 

 

 MicroZed Chronicles Second Year.jpg

 

 

 

You also can find links to all the previous MicroZed Chronicles blogs on my own Web site, here.

 

 

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About the Author
  • Be sure to join the Xilinx LinkedIn group to get an update for every new Xcell Daily post! ******************** Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.