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Adam Taylor’s MicroZed Chronicles, Part 118: VDMA Hardware

by Xilinx Employee on ‎02-08-2016 11:17 AM (38,635 Views)


By Adam Taylor



Now that we have the video test-pattern generator up and running, the next step is to insert the VDMA into our design. We are going to insert the VDMA between the test pattern generator and the AXI-Stream-to-Video-Output block.


The VDMA consists of independent write and read channels, allowing the block to write frames from the input video stream to a memory-mapped location or to read data from memory-mapped locations and send it to the AXI stream output. Typically, a number of frames will be stored in memory-mapped locations so that the video data can be manipulated (if desired) before the frame is output. An example of manipulation would be object-detection algorithms running on the PS (Processor System) side of the Zynq SoC.


We want to transfer the stream data to our DDR memory. To do this, we will connect to the High Performance port on the PS. Both the read and the write channels from the VDMA need to be connected to the High Performance port. We’ll add an AXI Interconnect block between the VDMA and the PS to make the connection.







The processor uses an AXI4-Lite interface to control the VDMA. We’ll connect this interface to the same General Purpose AXI interface that connects the PS to the test pattern generator.


I have kept the clocking architecture in this example very simple. All of the AXI peripherals run from fabric clock 0 at 100MHz. The video timing generator and the video output section of the AXI-Stream-to-Video-Output block run at a 40MHz pixel frequency provided by fabric clock 1.


I have also include a number of ILA blocks within the design to enable inspection and gain understanding of what is happening with the design:


  • ILA 0 connected to the Video Timing Generator H and V Sync Signals
  • ILA 1 connected to the AXI-Stream-to-Video-Output Syncs
  • ILA 2 connected to the AXI Stream output from the VDMA
  • ILA 3 connected to the AXI Stream to Video output status
  • ILA 4 connected to the AXI stream generated by the test pattern generator


Inserting the VDMA requires that we change the mode of operation on the AXI-Stream-to-Video-Output generator from master to slave.


When it comes to configuring the VDMA module, we need to be sure to set the output stream width correctly (24 bits). I left the number of frame buffers set to three but we can add many more if necessary.






I also configured the VDMA to allow unaligned transfers. This setting enables unaligned transfers to the AXI memory-mapped boundaries.







The final step was to connect the VDMA and Test pattern generator interrupts to the PS. I decided to use the shared PPI interrupts for this purpose and therefore added a concatenation block to combine the three interrupt sources and supply them to the Zynq interrupt port.


With all of this implemented, the next step is to look at how we write software to get the VDMA up and running and outputting frames.





Complete block diagram






Implemented design





The code is available on Github as always.


If you want E book or hardback versions of previous MicroZed chronicle blogs, you can get them below.




  • First Year E Book here
  • First Year Hardback here.




 MicroZed Chronicles hardcopy.jpg



  • Second Year E Book here
  • Second Year Hardback here



 MicroZed Chronicles Second Year.jpg




You also can find links to all the previous MicroZed Chronicles blogs on my own Web site, here.




by Observer richkeefe
on ‎01-01-2018 10:21 AM

 Hi Adam,


Do you have a high res version of the block diagram images, or perhaps the top level BD or TCL files? The posted image, "Complete block diagram" does not have very much detail to depict all the component features and connections you've used.


As always, thanks for you continued work to provide these tutorials.


Rich Keefe

by Observer taylo_ap
on ‎01-04-2018 12:12 PM



The image below is the largest resolution complete design I can grab. I have however uploaded a TCL file which recreates this block diagram to the github. If you source this TCL file in vivado tcl console it will recreate the block diagram, as this was created a long time ago it is in Vivado 2015.4 


Thanks for reading 





About the Author
  • Be sure to join the Xilinx LinkedIn group to get an update for every new Xcell Daily post! ******************** Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.