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Adam Taylor’s MicroZed Chronicles, Part 121: The MicroZed Embedded Vision Kit 7-Inch touch Screen Part II

by Xilinx Employee ‎03-07-2016 09:47 AM - edited ‎03-08-2016 07:07 AM (64,729 Views)

 

By Adam Taylor

 

 

With the MicroZed Embedded Vision Kit demo up and running, we now want to add the driver to our design so that we can output the test pattern on the display.

 

To do this we need to update our hardware design in Vivado, but we must first determine the needed changes. At a high level, we need to do two things: configure the design to output an 800x480-pixel image and output the resulting video stream using DisplayPort.

 

Rather helpfully, Avnet provides an IP module on their github page that will convert the parallel video we normally use for VGA into serialized DisplayPort information. All we have to do is download the HDL files and package them as IP within Vivado. We can then drop this packaged IP into our block diagram design.

 

The interface to the 7-inch touchscreen screen uses both I2C and DisplayPort. Initially, we will just use the DisplayPort to output an image and we won’t worry about the touchscreen aspect, which we will explore in a subsequent blog.

 

 

Image1.jpg

 

 

The interface expected by the flat screen display appears in the image above. The display expects four serialized lanes and a clock, which is an up-converted (multiplied) version of the pixel clock. In this case, the pixel clock is 33.33 MHz when working at 800x480 pixels. We will use two of the ZedBoard’s PMOD connectors for this interface.

 

Looking at the schematics for the PMOD connectors we use to connect the ZedBoard to the display, the first PMOD connector will send the serialized data lanes while the second PMOD connector supplies the clock, which is used to recover the pixel stream, and the I2C interface, to be used later for the touchscreen element.

 

 

Image2.jpg

 

I am going to add in the DisplayPort IP block to our block diagram and connect it to the output from the AXI4 Stream-to-Video Out block:

 

 

Image3.jpg

 

 

 

The clock in to the ALI controller runs at the pixel clock frequency of 33.33 MHz. We use the Zynq PS clock 1 to generate this pixel clock (changing it from the 40 MHz we previously used). The pixel clock is also used to clock the video timing generator and the AXIS stream to video output, as the display port controller contains a PLL we will clock those with the clock output from the controller module.

 

Additionally, as we want to change the image size in the hardware build, I have enabled the AXI interface on the video timing generator, which allows us to adjust everything relating to the output video using software configurations in SDK. Within our software application we can change the following:

 

  • Test Pattern Generation Size
  • Video Timing Generator parameters
  • Video DMA settings

 

This should enable us to get the software up and running so that we can display any image we require on the 7-inch display.

 

In the next article we will look at how we can create the software to correctly drive the display. Once that is complete, we’ll look at the image-capture side of the processing chain after porting this design to the MicroZed board based on a Xilinx Zynq Z-7020.

 

 

 

The code is available on Github as always.

 

If you want E book or hardback versions of previous MicroZed chronicle blogs, you can get them below.

 

 

 

  • First Year E Book here
  • First Year Hardback here.

 

 

 MicroZed Chronicles hardcopy.jpg

 

 

 

  • Second Year E Book here
  • Second Year Hardback here

 

 

 

 MicroZed Chronicles Second Year.jpg

 

 

You also can find links to all the previous MicroZed Chronicles blogs on my own Web site, here.

 

Comments
by Newbie trevor.crowley
on ‎03-13-2016 08:48 PM

Perhaps I am looking at the wrong respository, but when I follow the github link, the last MicroZed commit was in Nov 2015.  

 

Is there another place I should look to see the SDK source code?

 

Thanks.

by Observer taylo_ap
on ‎03-14-2016 12:18 PM

Trevor,

 

It appears to be a problem my end with commits not going through(I suspect due to a low internet link) let me try again oveer the next few days to sync it all up. 

 

In the mean time if you need anything urgetnly email me and I will do my best - aptaylor@theiet.org

 

Cheers 

 

Adam 

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About the Author
  • Be sure to join the Xilinx LinkedIn group to get an update for every new Xcell Daily post! ******************** Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.