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Adam Taylor’s MicroZed Chronicles, Part 129: Incremental Compilation

by Xilinx Employee on ‎05-02-2016 10:32 AM (10,664 Views)

 

By Adam Taylor

 

 

Last week, we looked at Out-Of-Context Synthesis and the time it can save you. This week, I will explore the use of incremental compilation in the Xilinx Vivado HLx Design Suite’s implementation stage to shorten place-and-route times.

 

Incremental compilation allows us to use a design check point (DCP) from a reference to speed the overall design flow. A DCP reduces implementation time by using the previous placement and routing as a guide. This reuse preserves the previous quality of results within constraints. We’ll explore this later.

 

The theory behind incremental compilation is this: having implemented the design, we identify the need to make a change to its behavior through testing or because we want additional features and we’d prefer to save some time in the next design iteration. In a conventional design flow, we would re-synthesise the design and place-and-route it all over again, which takes a significant amount of time. Incremental compilation saves us time by only synthesizing, placing, and routing design modifications.

 

To use incremental compilation, we must first have a reference design. Typically this is a previously implemented design. We can then copy that existing project directory to create the reference. If the design is not a previous implementation, the DCP must be targeted at the same device and speed grade as the implementation target. The use of a reference DCP is required so that when we re-start the run in the current project, that run will be cleaned prior to the start of the new run. That’s why it’s not possible to re-use a DCP within the same run from the same project.

 

 

Image1.jpg

 

 

Incremental Compilation Flow

 

(Reference: Advanced FPGA Design Methodologies with Xilinx Vivado, Alexander Jäger, Computer Architecture Group, Heidelberg University, Germany)

 

 

We find the DCP we are looking for in the implementation folder, which we’ll find within the <project_name>.runs folder. Within the implementation folder—in this example called imp_1—you will find three Vivado Design Checkpoint Files:

 

 

  • <project_name>_opt.dcp
  • <project_name>_placed.dcp
  • <project_name>_routed.dcp

 

 

The content of these files is fairly straightforward. The first file contains the post-optimization DCP. The second file contains the post-placement DCP. The final file contains the DCP after the design has been routed. You’ll get the best results from the routed DCP.

 

Using this DCP file is very simple. Within Vivado, we open the implementation settings and point the incremental compile option box to the routed DCP file in our reference design.

 

 

Image2.jpg

 

Configuring the DCP to be used

 

 

Once we have configured the design to use the reference design’s DCP, we run the implementation and Vivado implements the design using the reference design as a starting point. I say starting point because the scope and impact of the design changes will affect the implementation and will determine whether or not we obtain maximum benefit from the incremental compilation, or if it can be used at all.

 

The changes we implement in the updated design will be functional, netlist-related, or both. If 95% of the cells and routing remain the same between reference and current implementation, we will gain maximum advantage from this approach. We’ll reduce implementation time and we’ll see the same quality of results that we saw with the reference.  Should the reference and new design share between 75% and 95% in common, we will still gain some benefit from the incremental implementation. Below 75% commonality, Vivado will implement the new design using the default settings and will not use the reference design. Vivado will place a warning in the log should this occur.

 

We can determine the levels of similarity by using Vivado’s report_incremental_reuse command while the implementation is open, as shown below:

 

 

Image3.jpg

 

Vivado Incremental Placement Report

 

 

Image4.jpg

 

Vivado Incremental Routing Report

 

 

You can learn more about incremental compilation in Xilinx User Guide UG904, Vivado Design Suite User Guide: Implementation, which provides detailed information on implementation and implementation strategies.

 

 

 

The code is available on Github as always.

 

If you want E book or hardback versions of previous MicroZed chronicle blogs, you can get them below.

 

 

 

  • First Year E Book here
  • First Year Hardback here.

 

 

MicroZed Chronicles hardcopy.jpg 

 

 

 

  • Second Year E Book here
  • Second Year Hardback here

 

 

MicroZed Chronicles Second Year.jpg 

 

 

 

You also can find links to all the previous MicroZed Chronicles blogs on my own Web site, here.

 

 

 

 

 

 

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About the Author
  • Be sure to join the Xilinx LinkedIn group to get an update for every new Xcell Daily post! ******************** Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.