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Adam Taylor’s MicroZed Chronicles, Part 153: SDSoC Performance & Tracing

by Xilinx Employee on ‎10-24-2016 12:12 PM (17,655 Views)

 

By Adam Taylor

 

Over the last few weeks and indeed last year, we have looked at the Xilinx SDSoC Development Environment in detail. However one area we have not examined are SDSoC’s performance monitoring and the trace capabilities.

 

Performance monitoring allows us to examine the performance of the processors executing applications within our system. We also can see the performance of the AXI interconnect used as part of the Zynq SoC’s PL acceleration in considerable detail. This feature allows us to understand the interaction between the PS and the PL. Tracing capability, which requires more detail, will be the focus of another blog.

 

We enable the AXI performance monitor using SDSoC’s Project overview. On the right-hand side under options, there is a tick box labeled Insert AXI Performance Monitoring. Checking this box and then cleaning the build, prior to a complete re-build of the project with the active configuration set to SDDebug, tells SDSoC to insert AXI performance-monitoring blocks into the design.

 

 

Image1.jpg

 

 

For this example, I will use one of the demo applications and target the ZedBoard. I am going to run the matrix multiplication example and target a bare-metal solution. We can monitor the AXI performance using both standalone code and Linux.

 

Once the application is built, we need to connect the ZedBoard to our development PC using both the UART and the JTAG connectors.

 

To run the examples on our target board, we will be using an approach that differs from what we have done before—i.e. we are not going to copy the generated files on to a SD Card. Instead we are going to use SDSoC’s Debugger. We will also be using two new perspectives within SDSoC: the debugger perspective (which should be familiar to those of us who have used Xilinx SDK previously), and the performance analysis perspective.

 

The first thing we need to do with the files we’ve generated is to create a debug configuration for the elf file. Within SDSoC, under project explorer, open the folder for the project we have just compiled, expand the SDDebug folder, and select the elf file for the project.

 

 

Image2.jpg

 

 

 

Right click on this selection and select Debug As -> Debug Configurations. Create a new Xilinx SDSoC Application as configured in the image below.

 

 

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Selecting the Debug Configuration

 

 

 

On the application tab, check the stop program at entry operation. This will prevent the program from running the minute it is downloaded and will allow us to control the program when executed.

 

 

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SDSoC Debug Configuration

 

 

 

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Ensuring the program waits at entry

 

 

With this complete, click on debug. The bit file will be loaded and the application downloaded and held at the entry point, awaiting our command. You may see a dialog asking you to switch to the debug view, click yes and you will see that the application has been loaded and is paused.

 

 

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Program downloaded and awaiting execution

 

 

If we want to execute the program, we can click the resume button (or hit F8) as shown above. However if we do that, we will not obtain the performance data. If we want the performance data, we need to open the performance analysis perspective by clicking on the open perspective button.

 

 

Image7.jpg 

 

We can also select Window->Perspective-> Open Perspective-> Other

 

 

 

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Selecting the Performance Analysis Perspective

 

 

This will open the performance analysis perspective. However, before we can obtain the performance analysis, we need to define the underlying hardware. This is very simple to do under the performance system manager. Just select run.

 

 

Image9.jpg

 

The Performance Session Manager settings

 

 

This will open a dialog box that allows us to define the clock rate and the APM (AXI Performance Monitor) information. This information resides in the following directory:

 

 

<project>\SDDebug\_sds\p0\ipi\<projectname>.sdk\<projectname>.hdf

 

 

 

Image10.jpg

 

 

Defining the APM slots in the design

 

 

Once this is completed, we can run the program and capture the information of interest within in the performance graphs. These performance graphs relate to either the PS or the APM performance. I captured the following when I ran the program:

 

 

 

Image11.jpg

 

 

Result of the APM Performance Analysis Graph

 

 

 

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Result from the APM Performance Analysis Counters

 

 

 

Performance analysis allows us to examine the performance of our system in more depth, which helps us better understand the interaction between the Zynq SoC’s PS and PL.

 

 

 

Code is available on Github as always.

 

If you want E book or hardback versions of previous MicroZed chronicle blogs, you can get them below.

 

 

 

  • First Year E Book here
  • First Year Hardback here.

 

 

 

 MicroZed Chronicles hardcopy.jpg

 

 

  • Second Year E Book here
  • Second Year Hardback here

 

 

 

MicroZed Chronicles Second Year.jpg 

 

 

 

All of Adam Taylor’s MicroZed Chronicles are cataloged here.

 

 

 

 

 

 

 

 

 

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About the Author
  • Be sure to join the Xilinx LinkedIn group to get an update for every new Xcell Daily post! ******************** Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.