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Adam Taylor’s MicroZed Chronicles, Part 182: The XADC’s External Mux

by Xilinx Employee on ‎04-03-2017 10:35 AM (162,367 Views)

 

By Adam Taylor

 

We have looked at the XADC several times within this series. One thing we have not examined is how to use the external analog multiplexer capability. This is an oversight on my part as it can be very useful when we are architecting our system. With the XADC we can interface with up to 17 analog inputs: one dedicated Vp/Vn pair of inputs and sixteen auxiliary differential input pairs which share pins with the logic IO. This means that we can sample up to 17 different analog signals along with the device’s on-chip supply voltages and temperatures. This does of course does require the use of as many as 34 I/O pins, which can be challenging on some pin-constrained devices or designs.

 

The use of an external multiplexor provides us with the ability to sample up to 16 analog inputs. We need only 4 I/O lines for the multiplexer address as the Vp/Vn pair are dedicated and are outside of the multiplexer address. Note that we are not limited to using only the Vp/Vn pair for analog inputs.  You can use any of the auxiliary inputs as well.

 

To demonstrate how we do this, the first thing with need is a Vivado design with the XADC set up to allow an external mux. We can do this on the ADC setup tab of the XADC wizard. We can also select which analog inputs are being used with the external mux. If we already have a design with the XADC enabled, we can use the AXI interface to configure it.

 

 

Image1.jpg

 

 

 

With the wider Vivado design, I am going to include some ILAs (Integrated Logic Analyzers) so that we can see what is happening internally and I am going to connect the mux pins from the FPGA to the ZedBoard AMS header GPIO pins and into a logic analyzer so that we can see they are changing as would be the case when driving an external mux.

 

 

Image2.jpg 

 

 

Implementing this within the software is very similar to how we previously did this for the XADC. The first step is to configure the XADC as we would if we were using the internal mux capability. However, when we want to use the external mux we need to consider the information within UG480 and particularly the diagram below:

 

 

Image3.jpg 

 

 

To use an external mux, we therefore need to do the following in addition to our normal approach:

 

  1. Set the channel sequencer to cycle through the auxiliary channels we require. (We do not need to have all 16 channels enabled.) We do this using the same function as before using XSysMon_SetSeqChEnables() where the channels are defined using the XSM_SEQ_CH_xxx macros within xsysmon_hw.h.

 

  1. Inform the XADC which channel is connected to the external mux. In this case it is the VP / VN channel. We do this using the function XSysMon_SetExtenalMux(SysMonInstPtr,XSM_CH_VPVN), which defines the channel connected.

 

 

Once these have been configured, we set the XADC sampling by setting the sequencer mode to continuous pass.  This will then sequence the external mux pins around the inputs desired as shown below in the ILA capture when all 16 aux inputs are sampled.

 

 

Image4.jpg

 

 

 

The eagle-eyed will have noticed there are 16 external inputs which requires 4 pins but the external mux address provides 5 pins. To connect these to an external multiplexer we need to connect only the lower four bits of the address.

 

Just as we do when the internal mux is used, the sampled data from the conversion will be in the appropriate register and not in the Vp/Vn aux conversion register (e.g. aux 0 will be in aux 0, aux 1 in aux 1 and so on).

 

An external analog mux therefore allows us to monitor nearly the same number of analog signals with a much-reduced pin count. There is also another trick we can do with the XADC, which we will look, soon.

 

Code is available on Github as always.

 

If you want E book or hardback versions of previous MicroZed chronicle blogs, you can get them below.

 

 

 

  • First Year E Book here
  • First Year Hardback here.

 

 

MicroZed Chronicles hardcopy.jpg 

  

 

  • Second Year E Book here
  • Second Year Hardback here

 

 

MicroZed Chronicles Second Year.jpg

Comments
by Xilinx Employee
on ‎04-04-2017 06:00 AM

Glad you liked that feature. The other benefit is that can use a self-protecting or very robust (ESD/high voltage tolerant) external analog mux which is very useful in a harsh environment. Otherwise you end up using protecting resistors that can impact the acquisition time of the sampler and limit throughput.  

 

by Observer taylo_ap
on ‎04-04-2017 09:59 AM

Anthony that is a great example if any one wonders what they mean by the settling time then this blog here explains it 

 

https://forums.xilinx.com/t5/Xcell-Daily-Blog/Adam-Taylor-s-MicroZed-Chronicles-Part-104-XADC-with-Real-World/ba-p/659668

 

by Visitor se31berg
on ‎05-25-2017 07:59 AM

Hi

 

I am having difficulty connecting the ila_0 to the adc_wiz (M_AXIS), it won't allow me to make a connection there. Maybe I am missing something or I need to recustomize the IP? I'm not exactly sure what the issue is.

I have attached a picture of my current block design. Also if you notice anything else off with my design please let me know.

 

Thank you

VivadoXADC.png

by Observer taylo_ap
on ‎05-27-2017 02:44 AM

@se31berg

 

You need to re customise the IP block such that it can connect to native and not AXI interface that should solve the issue 

 

Adam 

by Observer taylo_ap
on ‎05-27-2017 02:59 AM

Correction you need to tell it that is is AXIS not AXI or native 

by Visitor se31berg
on ‎05-30-2017 06:14 AM

Ok great! I have the block design completed but now I am unsure which code to use. I didnt see one that clearly related to this on your github page.

by Visitor se31berg
on ‎05-30-2017 08:39 AM

Hello I was able to make all of the connections, I believe, but when I try and generate the bitstream I get the following errors:

ERROR.png

BlockDiagram.png

by Visitor se31berg
on ‎06-05-2017 10:42 AM

Also should the Vp/Vn port be made external?

On the Processing System is the USB 0 I/O peripheral necessary? I see that it is not connected to anything within your block design.

 

How would I

 

"Set the channel sequencer to cycle through the auxiliary channels we require. (We do not need to have all 16 channels enabled.) We do this using the same function as before using XSysMon_SetSeqChEnables() where the channels are defined using the XSM_SEQ_CH_xxx macros within xsysmon_hw.h."

and

"Inform the XADC which channel is connected to the external mux. In this case it is the VP / VN channel. We do this using the function XSysMon_SetExtenalMux(SysMonInstPtr,XSM_CH_VPVN), which defines the channel connected. "

 

using the provided functions? Is this done automatically?

 

This is how I've set up my XADC:

XADC1.png

XADC2.png

XADC3.png

by Observer taylo_ap
on ‎06-05-2017 10:52 AM

Hi 

 

With respect to the error below it is a constraint error you need to correct the IO standards in your XDC file 

 

but when I try and generate the bitstream I get the following errors:

ERROR.png

by Observer taylo_ap
on ‎06-05-2017 10:56 AM

With respect to your question above

 

yes VP/Vn does need to be made external along with all of your mux signals. IF you want to use Aux channels you need to enable them and make them external too. you can then use the SW to configure the mode of operation.

 

I have collated all my blogs on the XADC here it might be of help 

 

Adam 

by Visitor se31berg
on ‎06-06-2017 07:14 AM

I currently do not have a .xdc file for this project. I wasnt aware that we needed the constraints file in order to access the pins. If I were to make the constraints file what would I need to include for the external mux?

 

Again thanks for all your help and patience.

by Observer taylo_ap
on ‎06-06-2017 01:43 PM

Drop me an email to adam@adiuvoengineering.com and I will send you the example one I created 

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About the Author
  • Be sure to join the Xilinx LinkedIn group to get an update for every new Xcell Daily post! ******************** Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.