UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Adam Taylor’s MicroZed Chronicles Part 46: Using both of the Zynq SoC’s ARM Cortex-A9 Cores

by Xilinx Employee on ‎08-25-2014 09:20 AM (38,046 Views)

 

By Adam Taylor

 

 

So far everything we have looked at on the PS (processor system) side of the Zynq All Programmable SoC has used just the one ARM Cortex-A9 processor core (Core 0). However the PS side contains two processor cores and for many applications we will want to use both of the Zynq cores to get maximum performance. Using both Zynq processor cores for different tasks can be called Asymmetric Multiprocessing (AMP) and can involve any of the following combinations:

 

  • Different Operating Systems on Core 0 and Core 1
  • Operating System on Core 0, Bare Metal code on Core 1 (or vice versa)
  • Bare Metal code on both cores executing different programmes

 

There are two kinds of multicore processing: symmetric and asymmetric. Before we define the difference between the two, we first have to define what multiprocessing is:

 

“Multiprocessing is the use of more than one processor within a system. This can allow the execution of more than one instruction at the same time. However, it does not necessarily have to.”

 

The difference between symmetric and asymmetric multiprocessing is

 

  • Symmetric Multiprocessing runs a number of software tasks concurrently by distributing the processing load across a number of microprocessor cores
  • Asymmetric Multiprocessing uses specialized processors to run specific applications or runs specialized applications on identical processors

 

Over the next few blogs we are going to be looking at AMP on the Zynq SoC. Initially, we’ll look at two bare-metal applications, each running on a different core.

 

When one runs AMP on the Zynq SoC, one must consider that the Zynq processor cores have a mixture of both private and shared resources. Both processors have private L1 instruction and data caches, timers, and watchdogs along with shared interrupt controllers (with both shared and private interrupts). However interrupts on the Zynq are not so straightforward because each core in the PS is capable of interrupting itself, the other processor, or both processors using software interrupts, which are distributed via the Interrupt Controller Distribution.

The Zynq SoC also has a large number of shared resources of which common examples include I/O peripherals, On Chip Memory, the Interrupt Controller Distributor, the L2 Cache and system memory located within the DDR memory. The following diagram shows you some of these resources.

 

 

Zynq Block Diagram.png

 

 

We will be running the two processor cores from DDR memory so we must take great care to segment the address regions used by each processor. Addresses are determined via the linker scripts for each application. If we fail to do this, the applications running on different cores could interfere with each other’s operation.

 

We will also have to modify the files auto-generated by the SDK to get the system up and running. The first step will be to modify the first-stage boot loader in line with XAPP1079, which examines bare metal / bare metal AMP.

 

It is my intention to initially create a very simple system that we can expand upon once it’s up and running. The first application will have the Zynq SoC’s processor Core 0 communicating with the user over RS232 while Core 1 runs a pattern on the LEDS connected to the MicroZed IO Carrier Card. These two applications will run without interaction.

 

 

We’ll then progress to looking at how we can establish communication between processors using the on-chip memory along with how we can share resources between processors. Eventually we will progress from bare-metal code running on both processors to running operating systems on one or both processor cores.

 

 

Please see the previous entries in this MicroZed series by Adam Taylor:

 

 

Adam Taylor’s MicroZed Chronicles Part 44: MicroZed Operating Systems—FreeRTOS

 

Adam Taylor’s MicroZed Chronicles Part 43: XADC Alarms and Interrupts 

 

Adam Taylor’s MicroZed Chronicles MicroZed Part 42: MicroZed Operating Systems Part 4

 

Adam Taylor’s MicroZed Chronicles MicroZed Part 41: MicroZed Operating Systems Part 3

 

Adam Taylor’s MicroZed Chronicles MicroZed Part 40: MicroZed Operating Systems Part Two

 

Adam Taylor’s MicroZed Chronicles MicroZed Part 39: MicroZed Operating Systems Part One

 

Adam Taylor’s MicroZed Chronicles MicroZed Part 38 – Answering a question on Interrupts

 

Adam Taylor’s MicroZed Chronicles Part 37: Driving Adafruit RGB NeoPixel LED arrays with MicroZed Part 8

 

Adam Taylor’s MicroZed Chronicles Part 36: Driving Adafruit RGB NeoPixel LED arrays with MicroZed Part 7

 

Adam Taylor’s MicroZed Chronicles Part 35: Driving Adafruit RGB NeoPixel LED arrays with MicroZed Part 6

 

Adam Taylor’s MicroZed Chronicles Part 34: Driving Adafruit RGB NeoPixel LED arrays with MicroZed Part 5

 

Adam Taylor’s MicroZed Chronicles Part 33: Driving Adafruit RGB NeoPixel LED arrays with the Zynq SoC

 

Adam Taylor’s MicroZed Chronicles Part 32: Driving Adafruit RGB NeoPixel LED arrays

 

Adam Taylor’s MicroZed Chronicles Part 31: Systems of Modules, Driving RGB NeoPixel LED arrays

 

 Adam Taylor’s MicroZed Chronicles Part 30: The MicroZed I/O Carrier Card

 

Zynq DMA Part Two – Adam Taylor’s MicroZed Chronicles Part 29

 

The Zynq PS/PL, Part Eight: Zynq DMA – Adam Taylor’s MicroZed Chronicles Part 28  

 

The Zynq PS/PL, Part Seven: Adam Taylor’s MicroZed Chronicles Part 27

 

The Zynq PS/PL, Part Six: Adam Taylor’s MicroZed Chronicles Part 26

 

The Zynq PS/PL, Part Five: Adam Taylor’s MicroZed Chronicles Part 25

 

The Zynq PS/PL, Part Four: Adam Taylor’s MicroZed Chronicles Part 24

 

The Zynq PS/PL, Part Three: Adam Taylor’s MicroZed Chronicles Part 23

 

The Zynq PS/PL, Part Two: Adam Taylor’s MicroZed Chronicles Part 22

 

The Zynq PS/PL, Part One: Adam Taylor’s MicroZed Chronicles Part 21

 

Introduction to the Zynq Triple Timer Counter Part Four: Adam Taylor’s MicroZed Chronicles Part 20

 

Introduction to the Zynq Triple Timer Counter Part Three: Adam Taylor’s MicroZed Chronicles Part 19

 

Introduction to the Zynq Triple Timer Counter Part Two: Adam Taylor’s MicroZed Chronicles Part 18

 

Introduction to the Zynq Triple Timer Counter Part One: Adam Taylor’s MicroZed Chronicles Part 17

 

The Zynq SoC’s Private Watchdog: Adam Taylor’s MicroZed Chronicles Part 16

 

Implementing the Zynq SoC’s Private Timer: Adam Taylor’s MicroZed Chronicles Part 15

 

MicroZed Timers, Clocks and Watchdogs: Adam Taylor’s MicroZed Chronicles Part 14

 

More About MicroZed Interrupts: Adam Taylor’s MicroZed Chronicles Part 13

 

MicroZed Interrupts: Adam Taylor’s MicroZed Chronicles Part 12

 

Using the MicroZed Button for Input: Adam Taylor’s MicroZed Chronicles Part 11

 

Driving the Zynq SoC's GPIO: Adam Taylor’s MicroZed Chronicles Part 10

 

Meet the Zynq MIO: Adam Taylor’s MicroZed Chronicles Part 9

 

MicroZed XADC Software: Adam Taylor’s MicroZed Chronicles Part 8

 

Getting the XADC Running on the MicroZed: Adam Taylor’s MicroZed Chronicles Part 7

 

A Boot Loader for MicroZed. Adam Taylor’s MicroZed Chronicles, Part 6 

 

Figuring out the MicroZed Boot Loader – Adam Taylor’s MicroZed Chronicles, Part 5

 

Running your programs on the MicroZed – Adam Taylor’s MicroZed Chronicles, Part 4

 

Zynq and MicroZed say “Hello World”-- Adam Taylor’s MicroZed Chronicles, Part 3

 

Adam Taylor’s MicroZed Chronicles: Setting the SW Scene

 

Bringing up the Avnet MicroZed with Vivado

 

 

 

 

Comments
by Explorer
on ‎08-25-2014 12:37 PM

hi Adam,

 

i follow all steps on XAPP1078 and XAPP1079 , but it seem, the instructor use another combination of xilinx file, to run AMP application on both cores, whitch can modify or make my project unusefull,

 

i created 2 bare-metal application, one for each cores, the problem is the commnication between those application, and using MOC seem difficult ( i can't found tutorial ), and other thing is the use of shared ressource like UART ??

 

can we make AMP system with communication between both cores, without use of XAPP 1079 method ?, in other way, without use the reposity configuration, camming with XAPP1079, used in previous xilinx document ?

 

one think, whitch i proposed for the next blog, is how the first application ( core 0),  can get private information from second application ( core ).

 

last thing, is the bootable version of this AMP application, i meeted problem after generation of FSBL, i can't found instruction to modofy the boot file lscript.ld ?

 

thank you

 

 

by Observer taylo_ap
on ‎08-26-2014 10:39 AM

Hi GMA

 

I will be looking at communication between them and how we use shared resourceslike UARTS. 

 

I have found that using XAPP1079 (1078) as the base for AMP to be the simplest and fastest way to get this system up and running the key points required are the modified FSBL to look for the second elf file and a modified stand alone OS for the core 1 BSP. 

 

the example I have does run from a SD card, following  power on or reset the system boots up and starts executing both cores as it should

 

Adam 

Labels
About the Author
  • Be sure to join the Xilinx LinkedIn group to get an update for every new Xcell Daily post! ******************** Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.