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Adam Taylor’s MicroZed Chronicles Part 66: AXI DMA

by Xilinx Employee on ‎01-26-2015 10:27 AM (26,385 Views)

 

By Adam Taylor

 

My most recent blog posts have examined how to address the Zynq SoC’s XADC block over the internal AXI interface in the Zynq PS (processing system) and how you can debug and profile your applications. One interesting aspect of the Zynq SoC we have not looked at yet is the ability to move data from the PL (programmable logic) section into memory that’s mapped within the PS address space—into on-chip memory or DDR SDRAM for instance.

 

As engineers we will often want to do this. Putting the memory target for hardware implemented in the Zynq PL in the PS address space is very useful because doing so allows data transactions with that memory to be analyzed by the processors in the PS. The PS DMA engine will also be able to output the data from that memory over Ethernet and other I/O channels with minimal processor loading.

 

We have two choices of approach:

 

Using a general-purpose AXI port between the PL and the PS enables access to the PS DDR memory controller, as indicated by the red line in the diagram below.

 

 

Image1.jpg

 

 

The red path connects through the PS central interconnect so this approach also gives you the ability to access the I/O peripherals, Flash memory interfaces and even the master general-purpose AXI Ports in the PS.

 

Alternatively, you can use the high-performance AXI port as indicated by the red lines in the diagram below to store data in either on-chip memory or the attached DDR SDRAM through the SDRAM controller in the Zynq PS.

 

 

Image2.jpg

 

 

The “right” choice depends upon the data rates you need to transfer and the data’s end destination. The maximum achievable data rates are shown in the table below:

 

 

Image3.jpg

 

 

No matter which of these two approaches you use, the PS will be the slave and the PL will be the master. That’s different than the examples we’ve seen in previous instalments of the MicroZed Chronicles series.

 

It is very common to move data from the Zynq PL to the PS using DMA because DMA transfers maintain throughput while keeping processor overhead low. (Note: While an AXI DMA controller may be instantiated within the PL and may act as the master during data transfers, it will also have a slave AXI4-lite port that the processor in the Zynq PS will use to configure, start, and control the DMA transactions.)

 

Typically, high-performance cores instantiated within the Zynq PL will use an AXI streaming interface. AXI streaming has no address channel and therefore needs to be converted from AXI streaming into a memory-mapped AXI channel before it can be used to store data in a memory-mapped location. The normal method for accomplishing this is to use an AXI DMA block instantiated within the Zynq PL. This block is capable of reading and writing to and from AXI data streams.

 

Over the next few blogs we are going to explore how we implement a DMA block within the Zynq hardware and the software needed to get a device instantiated in the PL to stream data into DDR SDRAM mapped into the PS memory space for further processing by the ARM Cortex-A9 MPCore processors in the Zynq PS. One good example of why we would want to do this would be to enable testing of an ADC—to determine its SFDR and ENOB—for example. Computing these measurements helps to ensure that the PCB design is good for high-speed designs.

 

 

Please see the previous entries in this MicroZed Chronicles series by Adam Taylor:

 

Adam Taylor’s MicroZed Chronicles Part 65: Profiling Zynq Applications II

 

Adam Taylor’s MicroZed Chronicles Part 64: Profiling Zynq Applications

 

Adam Taylor’s MicroZed Chronicles Part 63: Debugging Zynq Applications

 

Adam Taylor’s MicroZed Chronicles Part 62: Answers to a question on the Zynq XADC

 

Adam Taylor’s MicroZed Chronicles Part 61: PicoBlaze Part Six

 

Adam Taylor’s MicroZed Chronicles Part 60: The Zynq and the PicoBlaze Part 5—controlling a CCD

 

Adam Taylor’s MicroZed Chronicles Part 59: The Zynq and the PicoBlaze Part 4

 

Adam Taylor’s MicroZed Chronicles Part 58: The Zynq and the PicoBlaze Part 3

 

Adam Taylor’s MicroZed Chronicles Part 57: The Zynq and the PicoBlaze Part Two

 

Adam Taylor’s MicroZed Chronicles Part 56: The Zynq and the PicoBlaze

 

Adam Taylor’s MicroZed Chronicles Part 55: Linux on the Zynq SoC

 

Adam Taylor’s MicroZed Chronicles Part 54: Peta Linux SDK for the Zynq SoC

 

Adam Taylor’s MicroZed Chronicles Part 53: Linux and SMP

 

Adam Taylor’s MicroZed Chronicles Part 52: One year and 151,000 views later. Big, Big Bonus PDF!

 

Adam Taylor’s MicroZed Chronicles Part 51: Interrupts and AMP

 

Adam Taylor’s MicroZed Chronicles Part 50: AMP and the Zynq SoC’s OCM (On-Chip Memory)

 

Adam Taylor’s MicroZed Chronicles Part 49: Using the Zynq SoC’s On-Chip Memory for AMP Communications

 

Adam Taylor’s MicroZed Chronicles Part 48: Bare-Metal AMP (Asymmetric Multiprocessing)

 

Adam Taylor’s MicroZed Chronicles Part 47: AMP—Asymmetric Multiprocessing on the Zynq SoC

 

Adam Taylor’s MicroZed Chronicles Part 46: Using both of the Zynq SoC’s ARM Cortex-A9 Cores

 

Adam Taylor’s MicroZed Chronicles Part 44: MicroZed Operating Systems—FreeRTOS

 

Adam Taylor’s MicroZed Chronicles Part 43: XADC Alarms and Interrupts 

 

Adam Taylor’s MicroZed Chronicles MicroZed Part 42: MicroZed Operating Systems Part 4

 

Adam Taylor’s MicroZed Chronicles MicroZed Part 41: MicroZed Operating Systems Part 3

 

Adam Taylor’s MicroZed Chronicles MicroZed Part 40: MicroZed Operating Systems Part Two

 

Adam Taylor’s MicroZed Chronicles MicroZed Part 39: MicroZed Operating Systems Part One

 

Adam Taylor’s MicroZed Chronicles MicroZed Part 38 – Answering a question on Interrupts

 

Adam Taylor’s MicroZed Chronicles Part 37: Driving Adafruit RGB NeoPixel LED arrays with MicroZed Part 8

 

Adam Taylor’s MicroZed Chronicles Part 36: Driving Adafruit RGB NeoPixel LED arrays with MicroZed Part 7

 

Adam Taylor’s MicroZed Chronicles Part 35: Driving Adafruit RGB NeoPixel LED arrays with MicroZed Part 6

 

Adam Taylor’s MicroZed Chronicles Part 34: Driving Adafruit RGB NeoPixel LED arrays with MicroZed Part 5

 

Adam Taylor’s MicroZed Chronicles Part 33: Driving Adafruit RGB NeoPixel LED arrays with the Zynq SoC

 

Adam Taylor’s MicroZed Chronicles Part 32: Driving Adafruit RGB NeoPixel LED arrays

 

Adam Taylor’s MicroZed Chronicles Part 31: Systems of Modules, Driving RGB NeoPixel LED arrays

 

 Adam Taylor’s MicroZed Chronicles Part 30: The MicroZed I/O Carrier Card

 

Zynq DMA Part Two – Adam Taylor’s MicroZed Chronicles Part 29

 

The Zynq PS/PL, Part Eight: Zynq DMA – Adam Taylor’s MicroZed Chronicles Part 28  

 

The Zynq PS/PL, Part Seven: Adam Taylor’s MicroZed Chronicles Part 27

 

The Zynq PS/PL, Part Six: Adam Taylor’s MicroZed Chronicles Part 26

 

The Zynq PS/PL, Part Five: Adam Taylor’s MicroZed Chronicles Part 25

 

The Zynq PS/PL, Part Four: Adam Taylor’s MicroZed Chronicles Part 24

 

The Zynq PS/PL, Part Three: Adam Taylor’s MicroZed Chronicles Part 23

 

The Zynq PS/PL, Part Two: Adam Taylor’s MicroZed Chronicles Part 22

 

The Zynq PS/PL, Part One: Adam Taylor’s MicroZed Chronicles Part 21

 

Introduction to the Zynq Triple Timer Counter Part Four: Adam Taylor’s MicroZed Chronicles Part 20

 

Introduction to the Zynq Triple Timer Counter Part Three: Adam Taylor’s MicroZed Chronicles Part 19

 

Introduction to the Zynq Triple Timer Counter Part Two: Adam Taylor’s MicroZed Chronicles Part 18

 

Introduction to the Zynq Triple Timer Counter Part One: Adam Taylor’s MicroZed Chronicles Part 17

 

The Zynq SoC’s Private Watchdog: Adam Taylor’s MicroZed Chronicles Part 16

 

Implementing the Zynq SoC’s Private Timer: Adam Taylor’s MicroZed Chronicles Part 15

 

MicroZed Timers, Clocks and Watchdogs: Adam Taylor’s MicroZed Chronicles Part 14

 

More About MicroZed Interrupts: Adam Taylor’s MicroZed Chronicles Part 13

 

MicroZed Interrupts: Adam Taylor’s MicroZed Chronicles Part 12

 

Using the MicroZed Button for Input: Adam Taylor’s MicroZed Chronicles Part 11

 

Driving the Zynq SoC's GPIO: Adam Taylor’s MicroZed Chronicles Part 10

 

Meet the Zynq MIO: Adam Taylor’s MicroZed Chronicles Part 9

 

MicroZed XADC Software: Adam Taylor’s MicroZed Chronicles Part 8

 

Getting the XADC Running on the MicroZed: Adam Taylor’s MicroZed Chronicles Part 7

 

A Boot Loader for MicroZed. Adam Taylor’s MicroZed Chronicles, Part 6 

 

Figuring out the MicroZed Boot Loader – Adam Taylor’s MicroZed Chronicles, Part 5

 

Running your programs on the MicroZed – Adam Taylor’s MicroZed Chronicles, Part 4

 

Zynq and MicroZed say “Hello World”-- Adam Taylor’s MicroZed Chronicles, Part 3

 

Adam Taylor’s MicroZed Chronicles: Setting the SW Scene

 

Bringing up the Avnet MicroZed with Vivado

 

 

 

Comments
by Visitor lion_time
on ‎02-07-2015 06:40 AM

Hi,Adam.Thank you for your introduction about the  AXI DMA.Recent ly, I have some questions on DMA when configure one DMA transfers data to  UART1(PS).

1. How to control the DMA transfer speed.Some other articles  say  " Burst Size and Burst Length".Then I try to change the two parameters,But the speed shows just with former.I also doesn' t understand their meaning clearly.

Some other chip use clock to control the DMA speed ,while i can't find this in the zynq dma.

2.Your paper shows the connected by AXI between DMA and XADC(PL),then between DMA and Uart 1(PS)(Does it need one AXI to connect each other?)

3. I test same Code with DMA  and non-DMA, DDR to DDR,the results shows speed doesn‘t improve much(improve about one quater 1 M bit Data).Is there something wrong with it?

 

May I get your some advice?

Thanks for  your  work !

                                                                                                                                     by lion

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About the Author
  • Be sure to join the Xilinx LinkedIn group to get an update for every new Xcell Daily post! ******************** Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.