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Adam Taylor’s MicroZed Chronicles Part 67: AXI DMA II

by Xilinx Employee on ‎02-02-2015 09:55 AM (83,581 Views)

By Adam Taylor

 

When we looked at the Zynq SoC’s AXI DMA last week, I explained how we could use an AXI DMA controller to move data from the PL to the PS. In this blog we will look at how we build hardware to do this.

 

The first thing to do is to understand a little more about the AXI streaming interface. The Vivado Design Suite AXI Reference Guide (User Guide 1037) rather helpfully provides detailed information on the the Zynq SoC’s AXI protocols. To create hardware for this example we will be using:

 

  • AXI4-Stream – High performance output from the Zynq SoC’s XDAC streaming to memory mapped port using DMA
  • AXI4-Lite – To configure and control the XADC and the DMA controller
  • AXI4 – To configure the FIFO adapter

 

These various uses will require two separate AXI buses—one that the PS controls as the master and another in which the PS is the slave.

 

The master PS AXI interconnect allows the PS to configure and control the XADC and DMA controller. These devices must be configured before transfers can occur. The slave PS AXI port allows the XADC data to be streamed and converted by the AXI DMA controller into a format suitable for memory-mapped transactions. The DMA is capable of transmitting data in either direction using these ports:

 

 

  • S/M_AXIS_S2MM – Slave/Master stream to memory map (device to DMA)
  • S/M_AXIS_MM2S – Slave / Master memory map to stream (DMA to device)

 

However due to a slightly different implementation of the AXI interface, the DMA controller requires the use of the optional input TLast. The XADC and the AXI DMA module cannot be directly connected, so an interface adapter is required to drive the optional TLast pin. Such an adapter already exists within the example code provided by XAPP1183 (“Implementing Analog Data Acquisition using the Zynq-7000 AP SoC Processing System with the XADC AXI Interface”). It is therefore rather straightforward to download the code example and add in the hard IP adapter to our IP catalog in Vivado.

 

 

Image1.jpg

 

 

 

With the IP adapter added to the IP catalog, we can easily insert this block between the XADC and the DMA port to create a hardware design as below:

 

 

 

 Image2.jpg

 

 

 

For this example, I have connected the DMA S2MM master output to the slave GP AXI input on the PS, which allows us to store the data in either OCM (on-chip memory) or off-chip DDR SDRAM. GP AXI is the correct interface to use here due to the required data transfer rates from the XADC.

 

While the DMA in this example only transfers data in one direction S2MM, the MM2S ports are there if transfer is needed in the other direction. These can be removed by customising the core and disabling the read channel.

 

In the next blog we will look at the software we need to drive this hardware.

 

Comments
by Adventurer
on ‎02-03-2015 12:29 AM

I follow the article very interested. Please post a High resolution schematic block diagram, you do not see very well in the picture.

 

Thanks very much.

 

Best Regards,

 

debugasm

by Visitor lion_time
on ‎02-07-2015 10:13 PM

Hi adam. Thanks for your introduction on DMA.Recently,I have some questions about DMAconfigure when i try to configure one DMAtransfer data to Uart1(PS).
1. How to control the DMA Speed.Some article say "Burst Size""Burst Length" .But i change two parameters and the result speed just similar.Some other chip use clock to control the DMA speed ,while i can't find relative clock in the zynq dma.
2. I test the speed on DMA and non-DMA,the speed also similar.Is there something wrong with it.
3.You say xadc(PL) and DMA connected by AXI.Then does Uart1(PS)and dma also connected by AXI?

by Xilinx Employee
on ‎02-10-2015 10:31 AM

lion_time,

 

Adam will respond to your question in a bit. He's traveling at the moment.

 

--Steve

 

by Observer taylo_ap
on ‎03-04-2015 11:39 AM

Lion_Time

 

I am still travelling ( I seem to be doing a lot at the moment) however, please see the answers below

 

Burst size and length will of course affect the speed of the transfer as will the clock at which you are running the DMA in the PL, this clock is your AXI Clock. There are four clocks which can be generated in the PS and passed to the PL enabling you to run things at different rate make sure you have correctly defined the clock constraints. 

 

If you look at figure 2-3 of the UG585 you will see how the MIO options are interconnected it shows which ones have DMA and the bus interconnection via the central interconnect as shown in figure 1-1 of the UG585. 

 

The user guide 585 has some really good, information I recommend all of the Zynq users have a copy easy to hand to use as a reference as needed

 

Adam 

by Visitor lion_time
on ‎03-10-2015 05:46 AM

Thank you for your reply And  your this Microzd Series.

 

I'll try the way you said.And read the relative UG.

 

look forward your mork relative nice articls.

 

Thanks a lot.

 

by lion_time.

by Visitor gongjian320
on ‎05-19-2015 05:10 PM

I follow the article very interested. Please post a High resolution schematic block diagram, such as export the system to a  pdf file, I can't see the signal names and connections in the picture !

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About the Author
  • Be sure to join the Xilinx LinkedIn group to get an update for every new Xcell Daily post! ******************** Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.