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Adam Taylor’s MicroZed Chronicles Part 85: SDSoC—the first instalment

by Xilinx Employee ‎06-08-2015 09:56 AM - edited ‎01-06-2016 02:06 PM (12,132 Views)

 

By Adam Taylor

 

When you stop and look at the history of FPGA development techniques since FPGA’s were first introduced in the mid-1980s, there has been an increasing trend to develop at a higher abstraction level; the new Xilinx SDSoC development environment continues this trend.

 

At first, FPGAs were developed schematically using standard logic gates and flip flops to implement required functions within the device. However this approach has several severe limitations when it comes to describing large designs and complex functionality, and for verification. It is much easier to describe the functionality you require at a higher level and allow the tool chain to determine the gate-level implementation. This is where Hardware Description Languages like Verilog and VHDL introduced a great advantage as they allowed us to program at a higher abstraction level where we describe the behavior we want to implement and the synthesis tools determine the actual logic.

 

Of course with HDLs we must code in specific ways and with constraints on supported commands if we wish the code to be synthesisable (although this does not apply for verification). As a result, much HDL development is performed at the Register Transfer Level (RTL). While HDLs have been the mainstay for a large number of years, increasing device capabilities, size, and performance mean that development of designs based on FPGAs and programmable SoCs using an HDL now faces the same issues schematic design did.

 

This all gets further complicated when we add SoCs like the Zynq into consideration. We want to ensure that we can maximize SoC performance by accelerating functions within the PL (programmable logic) side of the device. However we may not know until we are advanced in development if we have chosen all of the right functions for acceleration. Changes at a later stage will require further (unwelcome and potentially expensive) development time.

 

SDSoC enables us to not only significantly increase the level of abstraction as it builds upon the code generated by Vivado HLS but it also creates a tightly integrated development environment, which also allows us to effectively design the SoC application and achieve our system performance targets by accelerating selected functions within the device’s PL side. Moving functions into the PL from the PS (processor system) is very simple to do with the SDSoC development environment once we have determined which ones we wish to move. Then the build process creates the boot image in a single click.

 

Slick. Very slick.

 

Over the next few weeks, I am going to focus on SDSoC in this blog as we explore how it functions, how we can use it, and how it allows us to develop applications in C or C++ for our Zynq design.

 

As always with this blog, the best place to start is to provide a very simple overview of how the tool works. One of the first things I noticed when I opened the tool is that it is Eclipse-based and looks very familiar to the SDK we have been using to develop our SW applications to date.

 

 

Image1.jpg

 

 

SDK SoC Welcome Page

 

 

Image2.jpg

 

 

SDSoC Development environment

 

 

 

However, while similar there are a number of differences that we’ll explore in detail. At the very top level overview of SDSoC is as functions as follows:

 

  1. We develop our application in C or C++
  2. We profile the application to determine the performance bottle necks
  3. Using the profiling information we can identify functions to accelerate within the PL side of the device
  4. We can then build the system and generate the SD card image
  5. Once the hardware is on the board we can undertake analyse the performance further and optimise the acceleration functions as required

 

When we use SDSoC, we can chose either a bare-metal, FreeRTOS, or Linux operating system and SDSoC includes support for most of the Zynq development boards including the Zed, Avnet MicroZed, and Digilent Zybo.

This gives us a lot of very exciting things to look at over the upcoming weeks.

 

 

 

 Zynq 101 book cover.jpg

 

 

 

Now, you can have convenient, low-cost Kindle access to the first year of Adam Taylor’s MicroZed Chronicles for a mere $7.50. Click here.

 

Please see the previous entries in this MicroZed Chronicles series by Adam Taylor:

 

Adam Taylor’s MicroZed(ish) Chronicles Part 84: Simple Communication Interfaces Part 4

 

Adam Taylor’s MicroZed(ish) Chronicles Part 83: Simple Communication Interfaces Part 3

 

Adam Taylor’s MicroZed(ish) Chronicles Part 82: Simple Communication Interfaces Part 2

 

Adam Taylor’s MicroZed(ish) Chronicles Part 81: Simple Communication Interfaces

 

Adam Taylor’s MicroZed Chronicles Part 80: LWIP Stack Configuration

 

Adam Taylor’s MicroZed Chronicles Chronicles Part 79: Zynq SoC Ethernet Part III

 

Adam Taylor’s MicroZed Chronicles Chronicles Part 78: Zynq SoC Ethernet Part II

 

Adam Taylor’s MicroZed Chronicles Microzed Chronicles Part 77 – Introducing the Zynq SoC’s Ethernet

 

Adam Taylor’s MicroZed Chronicles Part 76: Constraints for Relatively Placed Macros

 

Adam Taylor’s MicroZed Chronicles, Part 75: Placement Constraints – Pblocks

 

Adam Taylor’s MicroZed Chronicles, Part 73: Physical Constraints

 

Adam Taylor’s MicroZed Chronicles, Part 73: Working with other Zynq-Based Boards

 

Adam Taylor’s MicroZed Chronicles, Part 72: Multi-cycle Constraints

 

Adam Taylor’s MicroZed Chronicles, Part 70: Constraints—Clock Relationships and Avoiding Metastability

 

Adam Taylor’s MicroZed Chronicles, Part 70: Constraints—Introduction to timing and defining a clock

 

Adam Taylor’s MicroZed Chronicles Part 69: Zynq SoC Constraints Overview

 

Adam Taylor’s MicroZed Chronicles Part 68: AXI DMA Part 3, the Software

 

Adam Taylor’s MicroZed Chronicles Part 67: AXI DMA II

 

Adam Taylor’s MicroZed Chronicles Part 66: AXI DMA

 

Adam Taylor’s MicroZed Chronicles Part 65: Profiling Zynq Applications II

 

Adam Taylor’s MicroZed Chronicles Part 64: Profiling Zynq Applications

 

Adam Taylor’s MicroZed Chronicles Part 63: Debugging Zynq Applications

 

Adam Taylor’s MicroZed Chronicles Part 62: Answers to a question on the Zynq XADC

 

Adam Taylor’s MicroZed Chronicles Part 61: PicoBlaze Part Six

 

Adam Taylor’s MicroZed Chronicles Part 60: The Zynq and the PicoBlaze Part 5—controlling a CCD

 

Adam Taylor’s MicroZed Chronicles Part 59: The Zynq and the PicoBlaze Part 4

 

Adam Taylor’s MicroZed Chronicles Part 58: The Zynq and the PicoBlaze Part 3

 

Adam Taylor’s MicroZed Chronicles Part 57: The Zynq and the PicoBlaze Part Two

 

Adam Taylor’s MicroZed Chronicles Part 56: The Zynq and the PicoBlaze

 

Adam Taylor’s MicroZed Chronicles Part 55: Linux on the Zynq SoC

 

Adam Taylor’s MicroZed Chronicles Part 54: Peta Linux SDK for the Zynq SoC

 

Adam Taylor’s MicroZed Chronicles Part 53: Linux and SMP

 

Adam Taylor’s MicroZed Chronicles Part 52: One year and 151,000 views later. Big, Big Bonus PDF!

 

Adam Taylor’s MicroZed Chronicles Part 51: Interrupts and AMP

 

Adam Taylor’s MicroZed Chronicles Part 50: AMP and the Zynq SoC’s OCM (On-Chip Memory)

 

Adam Taylor’s MicroZed Chronicles Part 49: Using the Zynq SoC’s On-Chip Memory for AMP Communications

 

Adam Taylor’s MicroZed Chronicles Part 48: Bare-Metal AMP (Asymmetric Multiprocessing)

 

Adam Taylor’s MicroZed Chronicles Part 47: AMP—Asymmetric Multiprocessing on the Zynq SoC

 

Adam Taylor’s MicroZed Chronicles Part 46: Using both of the Zynq SoC’s ARM Cortex-A9 Cores

 

Adam Taylor’s MicroZed Chronicles Part 44: MicroZed Operating Systems—FreeRTOS

 

Adam Taylor’s MicroZed Chronicles Part 43: XADC Alarms and Interrupts 

 

Adam Taylor’s MicroZed Chronicles MicroZed Part 42: MicroZed Operating Systems Part 4

 

Adam Taylor’s MicroZed Chronicles MicroZed Part 41: MicroZed Operating Systems Part 3

 

Adam Taylor’s MicroZed Chronicles MicroZed Part 40: MicroZed Operating Systems Part Two

 

Adam Taylor’s MicroZed Chronicles MicroZed Part 39: MicroZed Operating Systems Part One

 

Adam Taylor’s MicroZed Chronicles MicroZed Part 38 – Answering a question on Interrupts

 

Adam Taylor’s MicroZed Chronicles Part 37: Driving Adafruit RGB NeoPixel LED arrays with MicroZed Part 8

 

Adam Taylor’s MicroZed Chronicles Part 36: Driving Adafruit RGB NeoPixel LED arrays with MicroZed Part 7

 

Adam Taylor’s MicroZed Chronicles Part 35: Driving Adafruit RGB NeoPixel LED arrays with MicroZed Part 6

 

Adam Taylor’s MicroZed Chronicles Part 34: Driving Adafruit RGB NeoPixel LED arrays with MicroZed Part 5

 

Adam Taylor’s MicroZed Chronicles Part 33: Driving Adafruit RGB NeoPixel LED arrays with the Zynq SoC

 

Adam Taylor’s MicroZed Chronicles Part 32: Driving Adafruit RGB NeoPixel LED arrays

 

Adam Taylor’s MicroZed Chronicles Part 31: Systems of Modules, Driving RGB NeoPixel LED arrays

 

 Adam Taylor’s MicroZed Chronicles Part 30: The MicroZed I/O Carrier Card

 

Zynq DMA Part Two – Adam Taylor’s MicroZed Chronicles Part 29

 

The Zynq PS/PL, Part Eight: Zynq DMA – Adam Taylor’s MicroZed Chronicles Part 28  

 

The Zynq PS/PL, Part Seven: Adam Taylor’s MicroZed Chronicles Part 27

 

The Zynq PS/PL, Part Six: Adam Taylor’s MicroZed Chronicles Part 26

 

The Zynq PS/PL, Part Five: Adam Taylor’s MicroZed Chronicles Part 25

 

The Zynq PS/PL, Part Four: Adam Taylor’s MicroZed Chronicles Part 24

 

The Zynq PS/PL, Part Three: Adam Taylor’s MicroZed Chronicles Part 23

 

The Zynq PS/PL, Part Two: Adam Taylor’s MicroZed Chronicles Part 22

 

The Zynq PS/PL, Part One: Adam Taylor’s MicroZed Chronicles Part 21

 

Introduction to the Zynq Triple Timer Counter Part Four: Adam Taylor’s MicroZed Chronicles Part 20

 

Introduction to the Zynq Triple Timer Counter Part Three: Adam Taylor’s MicroZed Chronicles Part 19

 

Introduction to the Zynq Triple Timer Counter Part Two: Adam Taylor’s MicroZed Chronicles Part 18

 

Introduction to the Zynq Triple Timer Counter Part One: Adam Taylor’s MicroZed Chronicles Part 17

 

The Zynq SoC’s Private Watchdog: Adam Taylor’s MicroZed Chronicles Part 16

 

Implementing the Zynq SoC’s Private Timer: Adam Taylor’s MicroZed Chronicles Part 15

 

MicroZed Timers, Clocks and Watchdogs: Adam Taylor’s MicroZed Chronicles Part 14

 

More About MicroZed Interrupts: Adam Taylor’s MicroZed Chronicles Part 13

 

MicroZed Interrupts: Adam Taylor’s MicroZed Chronicles Part 12

 

Using the MicroZed Button for Input: Adam Taylor’s MicroZed Chronicles Part 11

 

Driving the Zynq SoC's GPIO: Adam Taylor’s MicroZed Chronicles Part 10

 

Meet the Zynq MIO: Adam Taylor’s MicroZed Chronicles Part 9

 

MicroZed XADC Software: Adam Taylor’s MicroZed Chronicles Part 8

 

Getting the XADC Running on the MicroZed: Adam Taylor’s MicroZed Chronicles Part 7

 

A Boot Loader for MicroZed. Adam Taylor’s MicroZed Chronicles, Part 6 

 

Figuring out the MicroZed Boot Loader – Adam Taylor’s MicroZed Chronicles, Part 5

 

Running your programs on the MicroZed – Adam Taylor’s MicroZed Chronicles, Part 4

 

Zynq and MicroZed say “Hello World”-- Adam Taylor’s MicroZed Chronicles, Part 3

 

Adam Taylor’s MicroZed Chronicles: Setting the SW Scene

 

Bringing up the Avnet MicroZed with Vivado

 

 

 

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About the Author
  • Be sure to join the Xilinx LinkedIn group to get an update for every new Xcell Daily post! ******************** Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.