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BittWare’s CAPI DevKit puts OpenPOWER servers in touch with UltraScale FPGA-based hardware acceleration

by Xilinx Employee ‎04-06-2016 10:16 AM - edited ‎04-06-2016 10:19 AM (22,200 Views)

 

Ok, here’s the quick, quick, quick lowdown on the OpenPOWER CAPI spec: It’s a way to coherently link CPUs with memory, storage, and computing resources that does not use CPU threads to move data to and from these resources. That’s important for a couple of reasons. First, it’s more efficient. CAPI-attached accelerators can lock memory the same way that CPU threads do using a communications channel that exhibits much lower latency than is possible using conventional processor-to-accelerator protocols. Second, it’s economical. Server fees are based on per-core usage and, consequently, server customers prefer to use fewer threads on fewer CPUs if possible. CAPI permits them to shift data-moving threads off the CPUs.

 

That preamble helps to explain why today’s announcement by BittWare of a new CAPI Developer’s Kit that includes the company’s new XUSP3S accelerator card based on a Xilinx Virtex UltraScale VU095 FPGA is a big deal. This kit provides you with a fast, efficient way to connect a Xilinx UltraScale FPGA to a CAPI-enabled IBM POWER8 system.  The developer's kit includes the FPGA accelerator card, IBM Power Service Layer (PSL) IP to provide the connection to the POWER8 server CPU, CAPI host support library, and an example CAPI design.

 

 

Note: For more information about the XUSP3S PCIe Network Card, see “BittWare’s XUSP3S PCIe Network Card uses UltraScale FPGAs to support four 100 GbE or sixteen 25/10 GbE ports. More on the way.”

 

 

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  • Be sure to join the Xilinx LinkedIn group to get an update for every new Xcell Daily post! ******************** Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.