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CCIX Consortium develops Release1 of its fully cache-coherent interconnect specification, grows to 22 members

by Xilinx Employee ‎10-11-2016 06:33 AM - edited ‎10-11-2016 09:59 AM (23,936 Views)

 

The CCIX Consortium, which is developing a specification for Cache Coherent Interconnect for Accelerators (CCIX), announced today that it has tripled in size to 22 member companies and that the Release1 specification covering the physical, data-link, and protocol layers is now available to the consortium’s members. The CCIX consortium has chosen PCIe for the specification’s first transport layer, supporting several standard PCIe line rates (2.5, 8, and 16Gbps) with an additional high-speed 25Gbps option. However, the CCIX coherency protocol is actually agnostic of the link layer. At the existing PCIe line rates, this choice leverages the existing PCIe ecosystem including silicon, connectors, chip- and board-level design IP, and software. The faster 25Gbps rate will require something different.

 

CCIX simplifies the design of offload accelerators for hyperscale data centers by providing low-latency, high-bandwidth, fully coherent access to server memory. The specification employs a subset of full coherency protocols and is ISA-agnostic, meaning that the specification’s protocols are independent of the attached processors’ architecture and instruction sets. Full coherency is unique to the CCIX specification. It permits accelerators to cache processor memory and processors to cache accelerator memory.

 

The 22 member companies in the CCIX Consortium now include:

 

  • AMD *
  • Amphenol
  • ARM *
  • Arteris
  • Avery Design Systems
  • Broadcom Limited
  • Atos
  • Cadence Design Systems
  • Cavium
  • Huawei *
  • IBM *
  • Integrated Device Technology
  • Keysight Technologies
  • Mellanox technologies *
  • Micron Technology
  • NetSpeed Systems
  • Qualcomm Technologies *
  • Red Hat
  • Synopsys
  • Teledyne LeCroy
  • TSMC
  • Xilinx *

 

Note: The * by the company name denotes a founding member

 

 

CCIX is designed to provide coherent interconnection between server processors and hardware accelerators, memory, and among hardware accelerators as shown below:

 

 

CCIX Configurations.jpg

 

 

Sample CCIX Configurations

 

 

Typical applications for such accelerated systems include:

 

  • In-memory database processing
  • Data-center search
  • Intelligent network acceleration
  • Machine/Deep Learning
  • High-performance computing/supercomputing
  • 4G and 5G base stations
  • Mobile edge computing
  • Video analytics
  • Embedded computing

 

 

Contact the CCIX Consortium for more information about joining and getting access to the Release1 specification.

 

 

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About the Author
  • Be sure to join the Xilinx LinkedIn group to get an update for every new Xcell Daily post! ******************** Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.