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Curtiss-Wright’s Rugged, Pre-Architected, Mission-Specific Computer System Targets SDR, EW Applications

by Xilinx Employee ‎07-14-2017 02:48 PM - edited ‎07-14-2017 02:53 PM (12,449 Views)

 

Curtiss-Wright has just introduced the first member in a new family of rugged, pre-integrated, mission-specific management computer systems based on its line of COTS modules. This first family member targets SDR (software-defined radio) and EW (electronic warfare applications) and so it packs as many as four of the company’s VPX3-530 High-Speed Transceiver modules with either four 12-bit, 2Gsamples/sec or two 12-bit, 4Gsamples/sec ADCs and two 14-bit, 2.8Gsamples/sec (5.6Gsamples/sec with interpolation) DACs controlled by a Xilinx Virtex-7 690T FPGA that also provides user-programmable, real-time signal processing. An Intel-based processor board, clock generator module, and power supply complete the system’s electronic hardware complement and all modules are housed in a rugged MPMC-9354 chassis that looks like this:

 

 

 

Curtiss-Wright MPMC-9354 Rugged Chassis.jpg 

 

 

Curtiss-Wright MPMC-9354 Rugged Chassis

 

 

The system is fully qualified to MIL-STD-704F, MIL-STD-810, and MIL-STD-461 testing.

 

Here’s what the inside of the chassis looks like:

 

 

Curtiss-Wright MPMC-9354 Interior Detail.jpg 

 

 

The VPX3-530 High-Speed Transceiver module supports phase-coherent ADC sampling and DAC output across multiple cards when used with the XCLK1 synchronous clock source. Here’s a photo of the VPX-530 module, prominently showing the Virtex-7 690T FPGA:

 

 

Curtiss-Wright VPX-530 High-Speed Transceiver Module.jpg

 

Curtiss-Wright VPX3-530 High-Speed Transceiver module

 

 

 

And here’s a block diagram of the VPX3-530 module showing the FPGA, ADCs, DACs, and the module’s two banks of DDR3 SDRAM:

 

 

Curtiss-Wright VPX-530 High-Speed Transceiver Module Block Diagram.jpg

 

 

The digital section is essentially the Virtex-7 FPGA, which implement’s all of the module’s logic, the SDRAM, and the non-volatile memory.

 

 

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About the Author
  • Be sure to join the Xilinx LinkedIn group to get an update for every new Xcell Daily post! ******************** Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.