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DeePhi’s Zynq-based CNN processor is faster, more energy efficient than CPUs or GPUs

by Xilinx Employee ‎08-23-2016 04:06 PM - edited ‎08-23-2016 04:11 PM (51,834 Views)


Step right up folks, the Hot Chips show is unfolding this week at the Flint Center for the Performing Arts in Cupertino, California and DeePhi has rolled out a convolutional neural network (CNN) acceleration processor named Aristotle that is faster and more energy efficient than CPUs or GPUs performing the same tasks. Is DeePhi’s CNN Processor some sort of super ASIC based on carbon nanotubes or memristors and powered by Mr. Fusion? Nope.


DeePhi’s Aristotle CNN Processor is based on a Xilinx Zynq-7000 All Programmable SoC.





DeePhi Aristotle Processor Slide from Hot Chips 2016



According to this article on Nextplatform.com, DeePhi’s CEO and co-founder Song Yao said that “CPUs don’t have the energy efficiency, GPUs are great for training but lack ‘the efficiency in inference’, DSP approaches don’t have high enough performance and have a high cache miss rate and of course, ASICs are too slow to market—and even when produced, finding a large enough market to justify development cost is difficult.


“FPGA based deep learning accelerators meet most requirements. They have acceptable power and performance, they can support customized architecture and have high on-chip memory bandwidth and are very reliable.”


Yao reportedly said: “The FPGA based DPU platform achieves an order of magnitude higher energy efficiency over GPU on image recognition and speech detection.” He also said that “traditionally, FPGA based acceleration via hand coding took a few months; using OpenCL and the related tool chain brings that down to one month.”


DeePhi was launched in March, 2016 and leverages the results of work from teams at Stanford University and Tsinghua University.




About the Author
  • Be sure to join the Xilinx LinkedIn group to get an update for every new Xcell Daily post! ******************** Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.