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Everspin’s NVMe Storage Accelerator mixes MRAM, UltraScale FPGA, delivers 1.5M IOPS

by Xilinx Employee ‎11-18-2016 02:50 PM - edited ‎11-18-2016 09:52 PM (5,530 Views)

 

Everspin, “The MRAM Company,” took an off-the-shelf Alpha Data ADM-PCIE-KU3 PCIe accelerator card, loaded 1Gbyte of MRAM DIMMs on the card, reprogrammed the on-board Kintex UltraScale KU060 FPGA to create an MRAM-based NVMe controller, and got…

 

1.5M IOPS

 

 

From non-volatile, no-wearout-failure MRAM.

 

The folks at Alpha Data handed me a data sheet for the resulting Everspin NVMe card, the ES1GB-N02 Storage Accelerator, at this week’s SC16 conference in Salt Lake City. Here’s a scan of that data sheet:

 

 

Everspin MRAM Accelerator Data Sheet.jpg 

 

 

Everspin makes MRAMs with DDR3 pin-level interfaces, but these non-volatile memory devices have unique timing requirements that differ from the DDR3 SDRAM standard. It’s therefore relatively easy to create an MRAM-based DDR3 SODIMM that snaps right into the existing SDRAM socket on the Alpha Data ADM-PCIE-KU3 card. Modify the SDRAM controller in the Kintex UltraScale FPGA to accommodate the MRAM’s timing requirements and—voila!—you’ve created an MRAM storage accelerator card.

 

There’s a key point to be made about a product like this. The folks at Alpha Data likely never envisioned an MRAM-based storage accelerator when they designed the ADM-PCIE-KU3 PCIe accelerator card but they implemented their design using an advanced Xilinx UltraScale FPGA knowing that they were infusing flexibility into the design. Everspin simply took advantage of this built-in flexibility in a way that produced a really interesting NVMe storage product.

 

Isn’t that the sort of flexibility you’d like to have in your products?

 

 

(Note: MRAM is magnetic RAM.)

 

 

 

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About the Author
  • Be sure to join the Xilinx LinkedIn group to get an update for every new Xcell Daily post! ******************** Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.