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FPGA-based Edico Genome Dragen Accelerator Card for IBM OpenPOWER Server Speeds Exome/Genome Analysis by 60x

by Xilinx Employee ‎11-16-2015 08:07 PM - edited ‎01-06-2016 10:55 AM (33,754 Views)

 

The SC15 (Supercomputing 2015) exhibit floor opened up this evening in Austin, Texas and one of the first demos of FPGA-based acceleration I saw on the show floor was in the IBM booth. Gavin Stone, VP of Marketing for Edico Genome was showing a 50-60x speedup in exome/genome analysis using his company’s Dragen accelerator card, which is based on a Xilinx FPGA. Here’s a photo of the Dragen board:

 

 

Edico Genome Dragen Accelerator Board.jpg

 

Edico Genome Dragen Accelerator Card for Exome/Genome Analysis, based on a Xilinx 28nm FPGA

 

 

The Xilinx FPGA is in the center of the board, wearing the Dragen decal.

 

The Edico Genome Dragen card is plugged into an IBM OpenPOWER server and acts as an accelerator for the server’s POWER processor. Assembling an exome or genome from the fragmented data supplied by a DNA sequencer is like assembling a jigsaw puzzle consisting of many millions of overlapping and duplicate puzzle pieces. It’s quite an exercise in template matching and mapping within a very large database.

 

Below is a 3-minute video demo of the Edico Genome system in action. As Stone explains in this video, the FPGA-based Dragen card cuts exome processing time to about six minutes. Software-only exome processing requires about six hours, so the FPGA-based hardware acceleration is providing a 50x to 60x speedup:

 

 

 

 

Currently, the Edico Genome Dragen board is based on a 28nm Xilinx device. Stone told me the company is already considering a Xilinx UltraScale device for its next-generation board and hoping to get another 5x performance improvement. I wouldn’t bet against it.

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About the Author
  • Be sure to join the Xilinx LinkedIn group to get an update for every new Xcell Daily post! ******************** Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.