UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

GSI offers free IP to enable 7.2Gbytes/sec transfers in each direction between its SigmaQuad-IIIe SRAM and UltraScale FPGAs

by Xilinx Employee ‎09-20-2017 11:43 AM - edited ‎09-20-2017 02:54 PM (5,334 Views)

 

Got memory transfer-rate problems? Need more memory speed? GSI Technology may have an antidote for your problem in its SigmaQuad-IIIe SRAM, which is capable of transferring 7.2Gbytes/sec in both the read and write directions simultaneously when connected to a Xilinx Kintex UltraScale FPGA over separate, 36-bit read/write buses. That’s with an 800MHz clock rate.

 

How does GSI know this? The company has developed its own eval board to develop the memory controller IP needed to effect this nosebleed transfer rate and that IP is available free to GSI’s customers. (Contact GSI directly for more information.)

 

Here’s a photo of the GSI Eval Board with a SigmaQuad-IIIe SRAM connected to a Xilinx Kintex UltraScale KU040 FPGA:

 

 

 

GSI Quad SRAM Eval Board Ultrascale-SQ3e Small.JPG

 

GSI’s SigmaQuad-IIIe SRAM/Kintex UltraScale Eval Board

 

 

 

For more information, see this GSI brochure titled “Leading-Edge Memory Solutions for UltraScale & UltraScale+ FPGAs.” You might note from the brochure that GSI is already experimenting with Xilinx Kintex UltraScale+ FPGAs and their SigmaQuad-IVe SRAMs. Unsurprisingly, that combination goes even faster. More details when they’re available.

 

 

Labels
About the Author
  • Be sure to join the Xilinx LinkedIn group to get an update for every new Xcell Daily post! ******************** Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.