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Introduction to the Zynq Triple Timer Counter Part Two: Adam Taylor’s MicroZed Chronicles Part 18

by Xilinx Employee ‎02-03-2014 10:16 AM - edited ‎05-26-2015 04:30 PM (32,042 Views)

By Adam Taylor


In the last blog I introduced the very versatile triple timer counter in the Zynq All Programmable SoC’s Processing System (PS). This blog post shows you how to use the TTC to generate an output waveform. To do this we will need to use both the Vivado Design Suite and the SDK. In this blog post, we focus on what we need to do in Vivado.


The first thing to do is ensure that the TTC is enabled using the block diagram we created within Vivado. Make sure there’s a check mark in the TTC box.



Fig 1 Ensuring that the TTC is Enabled.jpg 


Figure 1: Ensuring that the TTC is enabled



Once we’re sure that the TTC is enabled, the next step is to ensure the TTC’s output is selected to be on the Extended MIO (EMIO) within the Programmable Logic (PL) side of the Zynq SoC because we’re going to be generating waveforms. We need to use the EMIO ports because the MIO locations available to both of the Zynq TTCs are already being used by the Ethernet, USB, and SD Card interfaces.


To use the EMIO, we need to select the EMIO option within the MIO configuration of the Zynq re-customization screen:



Fig 2 Selecting the IO for the Watchdog and TTC.jpg 


Figure 2: Selecting the I/O for the Watchdog and TTC



While we are within the re-customization dialog, we’ll also use the Clock Configuration page to set the TTC’s clock to the internal clock:




 Fig 3 Selecting the TTC drive clock.jpg


Figure 3: Selecting the TTC drive clock



Having completed both of these tasks, you can now close the re-customization window in Vivado. Now, you will notice that a number of new ports have appeared within the PS block in the Zynq SoC’s PS icon. These ports are for the TTC clock input and the TTC waveform outputs. Because we are only interested in using one of the three TTC waveform outputs in this example, we will only use the waveform output labelled TTC0_WAVE0_OUT.


The next step is to create an output port and connect it to the Zynq PS. This is as simple is right clicking within the Zynq PS icon in the Block Design window and selecting the Create Port option.




 Fig 4 Creating the Output Port.jpg


Figure 4: Creating the Output Port



Once you have named this port, connect it to the TTC_WAVE0_OUT output on the Zynq block diagram:




 Fig 5 Connecting the Output Port to the Zynq TTC Port.jpg


Figure 5: Connecting the Output Port to the Zynq TTC port



The port we are going to use is not within the Zynq SoC’s PS side. Therefore,  we need to create a constraint file to define which pin on the PL side of the device we will use for the TTC waveform output. We create a constraints file by selecting the constraints option within the Sources window, right clicking on constrs_1, and selecting Edit Constraints Sets:



 Fig 6 First Step in Creating the Constraints File.jpg


Figure 6: First step in creating the constraints file



As we do not currently have a constraints file, at the next dialog we must select Create New File as opposed to the Add Files option:



 Figure 7 Creating a new constraints file.jpg


Figure 7: Creating a new constraints file.



We get this Open File creation dialog:



Figure 8 Selecting the format and name.jpg


Figure 8: Selecting the format and name



Enter the desired file name for your constraints file and Vivado will open a blank constraints file, ready for editing. Vivado uses XDC formatting for constraints as opposed to the UCF formatting used with ISE. If you are unsure as to the new syntax, there is a helpful language template that you can use to explore and find the syntax needed for your XDC file.



 Figure 9 The Language template to help you write in the XDC format.jpg


Figure 9: The language template to help write in the XDC format



You can also find more help on the XDC format here.


For this example, we only need a very simple XDC file because we are using only one output, which will output the generated waveform on a micro header pin. Here were using pin R19, which is located on the back of the MicroZed board. This is pin is in a Zynq high range (HR) bank, which supports 3.3V I/O. High performance (HP) banks do not support voltage standards above 1.8V.


Here’s what our XDC file looks like:



 Figure 10 XDC pin constraints.jpg


Figure 10: XDC pin constraints


Once we have created this constraints file, we can implement the design and export it to SDK. Now we’re ready to write software to drive the timer. Before we export to SDK however, it’s first prudent to check that the EMIO pin is correctly placed on the pin desired using the IO Report:



 Figure 11 IO Report confirming pin placement.jpg


Figure 11: IO Report confirming pin placement




Please see the previous entries in this MicroZed series by Adam Taylor:


Introduction to the Zynq Triple Timer Counter Part One: Adam Taylor’s MicroZed Chronicles Part 17


The Zynq SoC’s Private Watchdog: Adam Taylor’s MicroZed Chronicles Part 16


Implementing the Zynq SoC’s Private Timer: Adam Taylor’s MicroZed Chronicles Part 15


MicroZed Timers, Clocks and Watchdogs: Adam Taylor’s MicroZed Chronicles Part 14


More About MicroZed Interrupts: Adam Taylor’s MicroZed Chronicles Part 13


MicroZed Interrupts: Adam Taylor’s MicroZed Chronicles Part 12


Using the MicroZed Button for Input: Adam Taylor’s MicroZed Chronicles Part 11


Driving the Zynq SoC's GPIO: Adam Taylor’s MicroZed Chronicles Part 10


Meet the Zynq MIO: Adam Taylor’s MicroZed Chronicles Part 9


MicroZed XADC Software: Adam Taylor’s MicroZed Chronicles Part 8


Getting the XADC Running on the MicroZed: Adam Taylor’s MicroZed Chronicles Part 7


A Boot Loader for MicroZed. Adam Taylor’s MicroZed Chronicles, Part 6 


Figuring out the MicroZed Boot Loader – Adam Taylor’s MicroZed Chronicles, Part 5


Running your programs on the MicroZed – Adam Taylor’s MicroZed Chronicles, Part 4


Zynq and MicroZed say “Hello World”-- Adam Taylor’s MicroZed Chronicles, Part 3


Adam Taylor’s MicroZed Chronicles: Setting the SW Scene


Bringing up the Avnet MicroZed with Vivado



About the Author
  • Be sure to join the Xilinx LinkedIn group to get an update for every new Xcell Daily post! ******************** Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.