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Is DDR4 the last SDRAM protocol? Yes, says SemiWiki’s Eric Esteve. Then what are the alternatives?

by Xilinx Employee ‎04-01-2014 01:37 PM - edited ‎04-01-2014 03:15 PM (26,423 Views)

What is an ASIC, SoC, or FPGA without external memory? Dead in the water.

 

SemiWiki’s Eric Esteve just published a blog titled “Bye-Bye DDRn Protocol?” Esteve admits that his assertion is provocative and he admits that “DDR4 will most probably be used for years.” That’s clear from Intel’s recent announcement on March 19 of DDR4 SDRAM support in future processors. Instead of just announcing “support” in future products, Xilinx has already demonstrated DDR4 operation with the new Kintex UltraScale All Programmable devices. (See “Ready for DDR4-2400? Need the bandwidth? Need the lower power consumption? Watch this 8-minute video.”)

 

Esteve further confirms the solid position that DDR4 SDRAM will have over the next several years. He writes “We may expect that DDR4 will be used in the enterprise market for the next two years, then in the Desktop PC segment when the DDR4 memory device price will have come down to the same level, or below DDR3 devices.” When that happens, you can expect DDR4 SDRAM to break into the embedded arena as well because by then, it will not only deliver the highest DRAM performance but the lowest per-bit cost as well.

 

Nevertheless, writes Esteve, “the '4' in DDRn will certainly be the latest of this kind…” [sic, I think Esteve means "last of this kind" from the context.]

 

Esteve published a great image showing evolution of DDR standards and maximum data rates over the past two decades:

 

DDR evolution.jpg 

 

 

What could replace DDR? Esteve has a preference: “...hopefully High Speed Serial SerDes based, with clock recovery to simplify both the SoC and the board level implementation.” There’s an example of such a memory already emerging. It’s called the Hybrid Memory Cube (HMC), a project under the auspices of the Hybrid Memory Cube Consortium. Xilinx is a founding developer member of the consortium, along with Micron and Open Silicon.

 

The HMC inserts a high-speed logic layer between the DRAM and the host processor or SoC. The logic layer manages the DRAM and makes the memory available to the system through four high-speed serial links, each requiring 16 high-speed serial transceivers (64 transceivers for a fully implemented interface). The SerDes ports on Xilinx Virtex-7 FPGAs fully supports the HMC’s 10Gbps and 12.5Gbps transceiver rates. With as many as 96 GTH transceivers per device, Xilinx 7 series FPGAs can easily leverage the high bandwidth of HMC devices. The GTH transceiver technology in Xilinx UltraScale FPGAs extends the HMC interface bandwidth to 15Gbps rates with 64 transceivers. The first commercial 2Gbyte HMC implementation is sampling from Micron with 160 Gbytes/sec of memory bandwidth.

 

(Note: The HMC released the first draft of its Gen2 specification to the consortium’s adopter members including Xilinx—with support for doubled data rates—in February of this year. Per the press release, Hugh Durdan, vice president of portfolio & solutions marketing at Xilinx. “Our UltraScale devices, which are currently shipping, were designed to support this specification and offer lower risk and faster time to market for high-bandwidth applications.”)

 

Similarly, MoSys’ Bandwidth Engine 2 is a device that adds fast-access memory to a system using multiple high-speed serial lanes to create an aggregate transfer rate of 250Gbps. (See “MoSys Bandwidth Engine 2 adds “Go Juice” to Kintex UltraScale FPGA via multiple 15.625Gbps lanes at OFC 2014.”)

 

None of that means that the brand new DDR4 memory interface is in any danger of disappearing any time soon. As Eric Esteve admits, DDR4 SDRAM will be here for years and its use will grow in the short- and medium-term future.

 

Future memory interfaces will certainly emerge. As they do, the All Programmable nature of Xilinx 7 series and UltraScale devices allow new memory types to be used in systems thanks to the flexible, programmable I/O and the ability to instantiate just about any required memory controller into the programmable-logic fabric of these devices.

 

Just in case you didn’t know, Xilinx has a Memory Interface Generator (MIG) tool that can automatically generate controllers and PHYs for many popular memory interfaces, and for mixed-interface designs where you have to control multiple memory types with the same device. Here’s a short video explaining the MIG tool:

 

 

 

 

 

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  • Be sure to join the Xilinx LinkedIn group to get an update for every new Xcell Daily post! ******************** Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.