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MeerKAT, forerunner of the SKA radio telescope, finds 1500 new galaxies using Virtex-7 FPGAs and HMC memory

by Xilinx Employee on ‎08-08-2017 01:30 PM (3,082 Views)


An article titled “FPGAs, OpenHMC Push SKA HPC Processing Capabilities” on the Nextplatform.com Web site describes the progress made by the 64-antenna MeerKAT radio telescope, predecessor to the Square Kilometer Array (SKA) radio telescope in South Africa. According to the article, MeerKAT has already discovered more than 1500 new galaxies. (According to a year-old media release on the MeerKAT site, the instrument’s first-light image showed more than 1300 new galaxies.) Each of the 64 MeerKAT antennas produces about 40Gbps of data, which means that the MeerKAT project needs a ton of processing power and a lot of fast memory. Xilinx Virtex-7 FPGAs in SKARAB (Square Kilometre Array Reconfigurable Application Board) computing platforms designed and made by Peralex provide the processing power.



MeerKAT Antenna.jpg


One of the 64 MeerKAT Radio Telescope Antennas



According to the Casper Wiki at the U. of Berkeley, SKARAB is an FPGA-centric computing cluster but it also seems to be the name of a 1U, rack-mountable box containing a Virtex-7 690T FPGA for high-speed DSP computation. Here’s a photo of the SKARAB’s main board:



SKARAB FPGA Processing Platform.jpg


SKARAB is an FPGA-centric computing cluster main board




The Virtex-7 FPGA resides in the center of the board and there are four mezzanine connectors on the board, as shown in the above photo. Each mezzanine connector links a mezzanine module to the Virtex-7 690T FPGA through sixteen 10.3125Gbps SerDes links, as shown in this SKARAB block diagram:




SKARAB FPGA Processing Platform Block Diagram.jpg 



SKARAB is an FPGA-centric computing cluster block diagram




As the block diagram shows, these mezzanine connectors with their aggregate 165Gbps throughput (in each direction) are used for a variety of analog and digital I/O and memory modules. According to the Nextplatform.com article, memory throughput was a real challenge so the design team is using HMC (Hybrid Memory Cube) memory for its extremely high throughput. HMC memory uses high-speed serial I/O to achieve that throughput. Communications between the Virtex-7 FPGA and HMC memory requires an HMC memory controller, which the SKARAB team obtained from the OpenHMC project started at the U. of Heidelberg. Conveniently, the OpenHMC controller is instantiated in the Virtex-7 FPGA itself.




Note: For more information about HMC memory in Xcell Daily, see:









About the Author
  • Be sure to join the Xilinx LinkedIn group to get an update for every new Xcell Daily post! ******************** Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.