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Meet the Zynq MIO: Adam Taylor’s MicroZed Chronicles Part 9

by Xilinx Employee ‎12-02-2013 12:51 PM - edited ‎05-26-2015 04:33 PM (25,087 Views)

By Adam Taylor

 

The last few blogs in the MicroZed Chronicles have focused upon getting the MicroZed up and running and looking at the Zynq SoC’s XADC. I thought it would be good in this blog to provide a little more detail on the Zynq SoC and how it works. This blog post focuses specifically on the Zynq SoC’s Multipurpose IO (MIO) block. It is this interface block that provides the Zynq SoC’s dual-core ARM Cortex-A9 MPCore processor with many standard interfaces. The MIO also contains the configuration settings that determine how the Zynq SoC boots.

 

Figure 1 Zynq Block Diagram with MIO.jpg 

 

The MIO connects to the PS (processor system) side of the Zynq SoC. It connects to 54 pins on Zynq devices (note that the Zynq-7010 SoC in the CLG225 package has 32 MIO pins), which are used for the following:

 

  • Defining the configuration method
  • Quad SPI memory interface
  • SRAM / NOR Flash memory interface
  • NAND Flash memory interface
  • Two 10/100/1000 Ethernet MACs
  • Two USB 2.0 OTG interfaces
  • Two SD Card interfaces
  • Two UARTs
  • Two master and slave I2C interfaces
  • Two full-duplex SPI interfaces
  • Two CAN 2.0B interfaces
  • PJTAG and TRACE debug interfaces
  • Triple timer/counter (TTC)
  • System watchdog timer

 

I think you will agree it is a pretty impressive list standard interfaces and devices. You will of course end up in a situation at times where you need to trade off the many interfaces with the available pin count. Engineering is, after all, always an art of compromise.

 

Using the Vivado design flow, you assign functions within the MIO by double clicking on the processor within your block diagram, which brings up the re-customize IP window. There are two options for defining the MIO. The first option—Peripheral I/O Pins—is very graphical and allows you to see how assigning one interface standard affects others, as shown in the image below:

 

Figure 2 Graphical MIO Definition.jpg 

 

You can also use this window to define the bank-voltage settings for each of the two I/O banks (green = active).

 

The second option is the “MIO Configuration” tab in the Zynq Processing System screen, shown below, which brings up a list of interfaces assigned to the MIO. We can also assign the EMIO pins in this view, which we will address in a little while.

 

Figure 3 MIO Configuration Window.jpg

 

 

The MIO is split into two voltage banks:

 

  1. MIO0 pins 0 to 15
  2. MIO1 pins 16 to 53

 

Bank 0 includes the configuration input pins, which are sampled following power up. These mode pins share the multiuse I/O pins on the PS side of the device. In all, there are seven mode pins mapped to MIO[8:2]. The first four mode pins define the boot mode; the fifth determines whether the PLL is used or not; and the sixth and seventh mode pins define the bank voltages on MIO bank 0 and bank 1 during power up. The voltage standard defined on MIO bank 0 and 1 can be changed from LVCMOS to HTSL following completion of the boot loader.

 

As mentioned above, at times there are not enough MIO pins to bring out all the interfaces you wish to have. In such cases, you can extend the MIO into the Programmable Logic (PL) side of the Zynq SoC. This is called Extended Multipurpose IO or EMIO. EMIO can provide up to 64 additional GPIO pins. Alternatively you can assign most of the MIO interfaces to the EMIO with the notable exception of the USB, SRAM/NOR memory interfaces, and the NAND Flash interface. The Zynq SoC technical reference manual provides very detailed information on the differences between MIO and EMIO capabilities. Assigning functions to the EMIO is very simple and is accomplished by clicking the EMIO button at the end of the Peripheral I/O Pins tab as shown below:

 

 

Figure 4 The Peripheral IO Pins Tab.jpg

 

 

The GPIO setting can be enabled and its size selected from the MIO Configuration option tab. The GPIO will be split into two banks of 32 bits each if the maximum 64-bit size is selected.

 

 

Figure 5 GPIO Setting.jpg

 

 

When you close the re-customize IP option, you will see that the additional ports you selected have been added to the PS within your block diagram:

 

Figure 6 PS Block Diagram.jpg 

 

The example above shows the PS when GPIO_0, SPI_0 TRACE_0, and TTC_0 are assigned to the EMIO. These functions can then be assigned as external IO and will be present within the re-generated HDL netlist.

 

Note: Because the EMIO is within the PL side of the Zynq SoC, do not forget to the enable the level shifters between the PS and PL to ensure correct operation.

 

This blog post is very relevant to the discussion of ATE ports and Zynq I/O capabilities described in the recent Xilinx Daily post “Are you incorporating standard interfaces in your DFT strategy to aid production ATE board testing? With Zynq?

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About the Author
  • Be sure to join the Xilinx LinkedIn group to get an update for every new Xcell Daily post! ******************** Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.