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Need fast, efficient, open-source PCIe DMA for your FPGA? RIFFA 2.2 from UCSD goes on GitHub

by Xilinx Employee ‎07-16-2015 09:57 AM - edited ‎01-06-2016 01:47 PM (11,317 Views)

PCIe has been an intra-system connection interface of choice for quite a while now, offering a standardized and well-understood way to move large amounts of data quickly between, for example, a host CPU and an FPGA. Efficient, high-speed PCIe screams for DMA and if that’s what you need, the latest version of RIFFA 2.2 (Reusable Integration Framework For FPGA Accelerators) is now posted on GitHub and includes DMA IP you might want for your current or your next design.


RIFFA 2.2 employs communication channels between software threads running on a CPU and hardware user cores instantiated on an FPGA. A channel is similar to a network socket in that it must be opened before it can be read and written. Then it must be closed. However, unlike a network socket, channel reads and writes be made simultaneous by using two threads. Each channel is independent and thread-safe. RIFFA 2.2 supports as many as twelve channels.


Here’s a block diagram of the RIFFA hardware/software architecture:



RIFFA Hardware Software Block Diagram.jpg



RIFFA Hardware/Software Architecture




But the real measure of a DMA controller is its ability to move data quickly and efficiently. According to the UCSD RIFFA Web page, the latest RIFFA versions are “able to saturate the PCIe link for nearly all link configurations supported.” The following chart shows the performance of designs based on RIFFA 2.1 using the 32 bit, 64 bit, and 128 bit interfaces:



 RIFFA Transfer Rates.jpg





For more detailed information about RIFFA, see the RIFFA 2.2 documentation and these two papers:


RIFFA: A Reusable Integration Framework for FPGA Accelerators


RIFFA 2.0: A Reusable Integration Framework for FPGA Accelerators





About the Author
  • Be sure to join the Xilinx LinkedIn group to get an update for every new Xcell Daily post! ******************** Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.