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Need to power a Xilinx FPGA, Zynq SoC, or Zynq UltraScale+ MPSoC? Avnet and Infineon have a free Webinar for you on January 16.

by Xilinx Employee on ‎01-11-2018 10:30 AM (14,642 Views)


Providing good, filtered, reliable, and precise power to FPGAs and SoCs is an engineering challenge and if you’d like help meeting with challenge for Xilinx FPGAs, Zynq SoCs, or Zynq UltraScale+ MPSoCs in the 10W to 50W range, then Avnet and Infineon’s January 16 Webinar titled “Infineon DC/DC PMIC for FPGAs/SoCs for 10W to 50W Applications” is for you.


Here are the key takeaways you should get from this free Webinar:



  • Learn to simplify your BOM by replacing many of your standard regulators with one Infineon PMIC


  • Learn how updating to Xilinx newest recommendations for rail power consolidation leads to best integration and use case


  • Discover how to re-use your power design to cover your complete set of application with FPGAs/SoCs and ASICs


  • Lower total solution cost by high level integration and component reduction (35% board area reduction)




Register here.

About the Author
  • Be sure to join the Xilinx LinkedIn group to get an update for every new Xcell Daily post! ******************** Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.