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New 14-minute video shows you how to set up Zynq UltraScale+ MPSoC PCIe as Root Port with Vivado, PetaLinux

by Xilinx Employee ‎04-07-2017 11:04 AM - edited ‎04-07-2017 11:10 AM (75,117 Views)


If you have a mere 14 minutes to spare, you can watch this new video that will show you how to set up the Zynq UltraScale+ MPSoC’s hardened, embedded PCIe block as a Root Port using the Vivado Design Suite. The target system is the ZCU102 eval kit (currently on sale for half price) and the video shows you how to use the PetaLinux tools to connect to a PCIe-connected NVMe SSD.


This is a fast, painless way to see a complete set of Xilinx development tools being used to create a fully operational system based on the Zynq UltraScale+ MPSoC in less than a quarter of an hour.





by Observer koolscooby
on ‎05-18-2017 02:20 PM

I wanted to add a couple of notes to help out others in case they have bugs/issues bringing up PCIe. 


In Vivado, the default settings of the Processing Subsystem block were incorrect for Root Port mode and I actually had to make a few changes to set them based on the screenshot on this Wiki.


I was receiving linux kernel PCIe error relating to address space allocation before I made the change:

[    2.166104] pci 0000:01:00.0: BAR 0: no space for [mem size 0x00100000 64bit pref]
[    2.173622] pci 0000:01:00.0: BAR 0: failed to assign [mem size 0x00100000 64bit pref]
[    2.181493] pci 0000:01:00.0: BAR 2: no space for [mem size 0x00100000 64bit pref]
[    2.189018] pci 0000:01:00.0: BAR 2: failed to assign [mem size 0x00100000 64bit pref]


At this point, PCIe would enumerate endpoint devices 50% of the time after boot. After a bit of debugging, I figured out a workaround from Linux: 

echo 1 > /sys/bus/pci/devices/0000\:00\:00.0/remove
devmem 0xFD1A0100
devmem 0xFD1A0100 w 0x28000
devmem 0xFD1A0100 w 0x08000
echo 1 > /sys/bus/pci/rescan



In addition, due to the way my custom hardware enables clocks (programmed after power up and after psu_init is called in the FSBL), I had to modify the FSBL template to use the appropriate MIO reset line (MIO31 on ZCU102 - but varies depending on your hardware design) and also reset the PCIe controller. You can make the previous devmem workaround permanent in the FSBL code after the clocks are stable and running, for example:

// Reset PCIe controller
RegVal = XFsbl_In32(0xFD1A0100);
XFsbl_Out32(0xFD1A0100, RegVal | 0x00020000);
// Run PCIe controller
RegVal = XFsbl_In32(0xFD1A0100);
XFsbl_Out32(0xFD1A0100, RegVal & 0xFFFDFFFF);

Hope this helps someone else!


About the Author
  • Be sure to join the Xilinx LinkedIn group to get an update for every new Xcell Daily post! ******************** Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.