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PLDA announces XpressRICH4-AXI PCIe 4.0 configurable IP for Xilinx Virtex-7, Virtex UltraScale, Kintex UltraScale devices

by Xilinx Employee on ‎03-15-2017 11:22 AM (36,732 Views)


PLDA has announced the XpressRICH4-AXI PCIe 4.0 configurable IP block that ties an on-chip AXI bus to PICe 4.0. The IP block complies with the PCI Express Base 4.0r7 specification and supports endpoint, root port, and dual mode configurations. The IP supports Xilinx Virtex-7, Virtex UltraScale, and Kintex UltraScale devices and can be used for ASIC design as well.


Here’s a block diagram of the core:



PLDA XpressRICH4-AXI PCIe 4 IP.jpg



PLDA XpressRICH4-AXI PCIe 4.0 configurable IP Block Diagram



Please contact PLDA directly for more information about this IP.



About the Author
  • Be sure to join the Xilinx LinkedIn group to get an update for every new Xcell Daily post! ******************** Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.