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PanaTeQ’s VPX3-ZU1 3U OpenVPX Module puts Zynq UltraScale+ MPSoC into the VPX Market

by Xilinx Employee on ‎01-23-2017 11:07 AM (35,301 Views)


Targeting military and other high-end, real-time computing applications, the PanaTeQ VPX3-ZU1 3U OpenVPX Module delivers the Xilinx Zynq UltraScale+ MPSoC with its six ARM processor cores (a quad-core ARM Cortex-A53 Application Processing Unit and a dual-core ARM Cortex-R5 Real-Time Processing Unit), an ARM MALI-400 Graphic Processing Unit, and big chunk of Xilinx’s advanced 16nm programmable logic available in the 100x160mm VPX form factor. The module also includes an on-board PCIe Gen2 switch driving eight PCIe ports on the VPX P1 port and an FMC site that complies with the Vita 57.1 HPC standard, which makes the VPX3-ZU1 board instantly compatible with a large number add-on I/O modules including the FMC-ZU1RF-A FMC Wideband RF Transceiver module based on the Analog Devices AD9371 Integrated, Dual RF Transceiver with Observation Path.




PanaTeq VPX3-ZU1 OpenVPX Module.jpg 



The VPX-ZU1 is available with one of three Xilinx Zynq UltraScale+ MPSoC devices (ZU6EG/ZU9EG/ZU15EG), and with either 2 or 4Gbytes of 64-bit DDR4-2400 SDRAM with 8-bit ECC for the Zynq UltraScale+ MPSoC’s processor system and either 512Mbytes or 1Gbyte of DDR4-2400 SDRAM connected to the Zynq UltraScale+ MPSoC’s programmable logic.


Here’s a detailed block diagram of the PanaTeQ VPX3-ZU1 3U OpenVPX Module:




PanaTeq VPX3-ZU1 Block Diagram.jpg 


PanaTeQ VPX3-ZU1 Block Diagram




PanaTeQ also offers the RTM-ZU1-A 3U OpenVPX Rear IO Transition Module for VPX3-ZU1, which makes the following I/O interfaces available on connectors through the rear-panel connectors:



  • 2x Ethernet 100/1000BaseT RJ-45 connectors
  • 2x USB 3.0 Type-A stacked connectors
  • 2x USB 2.0 Type-A stacked connectors
  • 1x mini Display Port 1.2 video output connector


And the following I/O interfaces on internal connectors:


  • 1x SATA 3.1 connector
  • 10x LVDS 20-pin flat-cable connector
  • 2x RS-232/422/485 + 2x CAN-Bus 10-pin flat-cable connector





About the Author
  • Be sure to join the Xilinx LinkedIn group to get an update for every new Xcell Daily post! ******************** Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.