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Pentek kicks its radar, SDR DSP architecture up a notch from Cobalt to Onyx to Jade by jumping to Kintex UltraScale FPGAs

by Xilinx Employee ‎11-01-2016 02:48 PM - edited ‎11-02-2016 12:05 PM (44,334 Views)

Pentek 71861 4-channel 200MHz ADC with DDC.jpg 

Pentek has taken proven DSP designs in its existing Cobalt and Onyx module product lines and migrated these designs to what the company is calling its Jade architecture based on 20nm Xilinx Kintex UltraScale FPGAs. As a result, according to Pentek, the modules based on the new Jade architecture deliver a 50% DSP performance boost while using 18% less power. There’s also a 39% cost reduction. Now that’s a technology migration story worth studying!

 

The first Pentek product to employ the Jade architecture is the Model 71861 XMC module with four 200MHz ADC channels and programmable multiband DDCs (digital downconverters). This module is designed for radar and software-defined radio applications. In addition to the XMC form factor, similar products are available in PCIe, 3U & 6U VPX, AMC, and 3U & 6U cPCI form factors. Pentek offers versions of these modules for both commercial and rugged environments.

 

Here’s a block diagram of the Pentek Model 78161 4-channel ADC module:

 

 

Pentek 71861 Block Diagram.jpg

 

Pentek Model 71861 Block Diagram

 

 

Note that the Kintex UltraScale FPGA implements every bit of the module’s digital system design except for the on-board Flash and DDR4 memory and the clock generator. The FPGA has access to all of the module’s data and control paths, permitting factory-defined functions to control the system’s data multiplexing, channel selection, data packing, gating, triggering, and the on-board acquisition and processing memory—which can be as large as 5Gbytes. All of these functions exist in the FPGA as IP blocks.

 

Here’s a block diagram of the IP design in the Pentek Model 71861 XMC module’s Kintex UltraScale FPGA:

 

 

Pentek 71861 FPGA Block Diagram.jpg 

 

Pentek Model 71861 FPGA Block Diagram

 

 

If this block diagram looks somewhat familiar, then perhaps you’re recalling similar block diagrams that appeared in this year’s July Xcell Daily blog post about Pentek’s Model 71791 L-band tuner in an XMC form factor and the earlier February Xcell Daily blog post about Pentek’s Cobalt 71664. (See “Pentek L-band Tuner XMC card handles 975-2175MHz RF with DDC and control help from a Virtex-7 FPGA” and “Virtex-6 FPGA powers Pentek VITA 49 Radio Transport Standard CompactPCI/AMC/PCIe/VPX Modules for SDR.”)

 

The titles of those blog posts along with the similar block diagrams tell you that Pentek has created three broad, board-level product generations by moving its IP—DDC, data packing, flow control, metadata generator, and DMA engine—from the Xilinx Virtex-6 FPGA family to the Virtex-7 FPGA family and on to the Kintex UltraScale FPGA family.

 

Pentek is not just spanning Xilinx FPGA generations with this latest product family based on its new Jade architecture, the company is taking advantage of the pin compatibility engineered into the Xilinx UltraScale FPGA product line to offer customers a range of products with different price/performance ratios.

 

More products = more choices for the customer.

 

As the Pentek press release states:

 

“The [modules'] Kintex UltraScale FPGA site can be populated with a range of FPGAs to match the specific requirements of the processing task, spanning the KU035 through KU115. The KU115 features 5520 DSP48E2 slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources or logic, a lower-cost FPGA can be installed.”

 

Now that’s true design reuse in action!

 

Note: For an additional discussion of ways to use Xilinx UltraScale device pin compatibility, see today’s earlier Xcell Daily post “PRO DESIGN adds five Virtex UltraScale modules and one Kintex UltraScale module to its growing FPGA prototyping line.”

 

 

 

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About the Author
  • Be sure to join the Xilinx LinkedIn group to get an update for every new Xcell Daily post! ******************** Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.