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Smart IOPS Data Engine SSD drops hammer on other NVMe SSDs with 1.7M IOPS: Powered by Kintex UltraScale FPGA

by Xilinx Employee ‎11-17-2016 09:37 AM - edited ‎11-17-2016 04:00 PM (46,462 Views)

 

This week at SC16 in Salt Lake City, Smart IOPS demonstrated its FPGA-powered Data Engine NVMe SSD, which delivers 1.7M IOPS—which the company claims is 4x that of competing NVMe SSDs. The secret, besides the embedded Xilinx Kintex UltraScale FPGA running the show in hardware, is Smart IOPS’ TruRandom technology, which uses pattern-recognition heuristics baked into the FPGA logic to speed read/write transactions between the host CPU and the Data Engine’s NAND Flash storage. This technology makes sustained random and sequential read/write transactions indistinguishable, meaning they run...

 

 

Fast

 

 

 

Smart IOPS Data Engine.jpg
 

 

Smart IOPS Data Engine NVMe SSD

 

 

 

Smart IOPS is offering the Data Engine NVMe SSD in 2 to 10Tbyte capacities and three flavors: T2, t2D, and T4. The T2 Data Engines employ 16nm MLC NAND Flash memory; the T2D Data Engines employ 3D MLC NAND Flash memory; and the T4 Data Engines employ 15nm MLC NAND Flash memory. The different types of flash affect the drives’ speeds as shown in these specs:

 

 

 

Smart IOPS specs.jpg

 

 

Smart IOPS Data Engine NVMe SSD specifications

 

 

 

Smart IOPS also packages one or more of its Data Engine SSDs in a rack-mounted Flash Appliance.

 

The on-board Xilinx Kintex UltraScale FPGA implements all of the functions in the Smart IOPS Data Engine including the PCIe Gen3 host interface; NAND Flash control; and of course the company’s proprietary, patent-pending, speed-multiplying TruRandom heuristics.

 

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About the Author
  • Be sure to join the Xilinx LinkedIn group to get an update for every new Xcell Daily post! ******************** Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.