We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

SystemVerilog RTL emulation of Yamaha OPL3 FM Synth chip runs on Zynq-based ZYBO board

by Xilinx Employee ‎07-27-2015 02:27 PM - edited ‎01-06-2016 01:40 PM (38,391 Views)

The Yamaha YMF262 OPL3 FM Sound Synthesis chip was popular as a sound generator for PC games back in the 1990s. Greg Taylor has reverse engineered the device and written a SystemVerilog RTL description targeting the low-cost Digilent ZYBO Development Board, which is based on a Xilinx Zynq Z-7010 SoC. The design consumes less than half of the programmable logic, very little on-chip RAM, and only one the 80 available DSP48 slices:



Yamaha OPL3 SystemVerilog Emulation Utilization.jpg



The SystemVerilog code’s on GitHub.


How does it sound? Listen for yourself (and dance in your chair):








About the Author
  • Be sure to join the Xilinx LinkedIn group to get an update for every new Xcell Daily post! ******************** Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.