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The 2015 Ross Freeman Award for Technical Innovation, Software: The SDAccel development environment

by Xilinx Employee ‎06-05-2015 09:25 AM - edited ‎01-06-2016 02:08 PM (27,553 Views)

Ivo Bolsens small.jpg

 

 

Last week, Xilinx CTO and Senior Vice President Ivo Bolsens presented two Ross Freeman Awards for Technical Innovation to the hardware and software innovation teams responsible for developing the relevant technologies. I interviewed Ivo after the awards to get more detail. This blog contains Ivo’s remarks about the software award, for the new Xilinx SDAccel development environment.

 

 

Ivo Bolsens:

 

What we are trying to do with the Ross Freeman Awards for Technical Innovation is recognize technical innovations—the technical contributions—that have reached the market in our products over the last fiscal year. That is, the technology that has reached our customers. These recognized innovations are a major differentiator in our products.

 

We’ve made these awards 23 times. In the past, there was only one award. Over time, as Xilinx has become more and more a software company, so recently we decided to give one award for hardware innovation and one for software innovation.

 

Sometimes, the problem you have at Xilinx is that the distinction between hardware and software is blurred because everything is programmable. What is hardware? What is software? You have silicon hardware. You have soft hardware. You have software running on soft hardware (code running on MicroBlaze processors, for example). You have software running on hard hardware (code running on the ARM Cortex-A9 MPCore processors in the Zynq SoC and MPSoC). It’s complicated.

 

The rule that we typically apply in the company is that if you have to FedEx it, it’s hardware; if you can email it, it’s software.

 

Now, what’s very important about the Ross Freeman Award for Technical Innovation is that the winners are selected by their technical peers at Xilinx. So in the end, the award decision rests not with a small group of Xilinx executives meeting in conclave. The executives select the finalists from nominations made by the Xilinx technical community, so getting nominated as one of the three top hardware or three top software innovations is an honor and recognition in itself.

 

It’s the Xilinx technical community that selects the award winners. I feel this is an important aspect of the award. Your peers are voting.

 

We also try to recognize the innovators. We know it takes a large team to get the technology into the product. Sometimes, selecting the innovators behind a technology is a difficult decision. You have to be almost in the mental model of writing a patent. Who are the people who really got it started? We’re not awarding the execution; we’re awarding the innovation and the idea. There are other places where execution can be rewarded.

 

This year, on the software side, we awarded the SDAccel technology, which won the popular vote just ahead of the SDSoC development environment. Both the SDAccel and SDSoC development environments have a software look and feel to make development with Xilinx All Programmable devices feel more familiar to people who specialize in software development.

 

 

Ross Freeman Award 2015 Software.jpg

 

2015 Ross Freeman Award for Technical Innovation, Software

 

 

The previous software-centric Ross Freeman Award for Technical Innovation winner was the high-level synthesis technology that is now at the heart of Vivado HLS. To a certain extent, that technology was a stepping stone to SDAccel, which has further developed the idea and the technology of high-level synthesis. Vivado HLS allows you to compile hardware from a high abstraction level, using C or C++, into functions implemented in an FPGA. But then, you need to surround these functions with an infrastructure, like the memory infrastructure and the I/O infrastructure, in the FPGA. So there’s still a hardware-development component when using Vivado HLS.

 

SDAccel adds an extra layer on top of Vivado HLS. SDAccel abstracts the model of a programmable platform—the memory interfaces, the interfaces between the CPU and the FPGA, the interfaces between the FPGA and the network, and so on. All of that is abstracted away by APIs that are made available in a parallel-programming environment, which is based on OpenCL.

 

The framework of OpenCL is built around the semantics of the OpenCL programming language. What OpenCL brings, on top of the original C programming language, is that it allows you to model the platform at a high level; it brings parallelism; and it brings run-time capabilities and reprogrammability to a platform.

 

By introducing OpenCL capabilities in our SDAccel environment, you can now look at the FPGA together with the CPU as a heterogeneous programming platform. You can write your run-time scheduling in OpenCL and you can write kernels, which are actually functions you implement on a CPU or FPGA. SDAccel then uses Vivado HLS to synthesize these functions into the FPGA fabric.

 

SDAccel is the next step, on top of Vivado HLS, to create that software look and feel for the software-development community. It’s an essential technology to move into the heterogeneous programming paradigm where you can take a high-level, software-centric description of your problem and map it onto a parallel platform that consists of heterogeneous components that execute the functions. We think this is an essential technology.

 

One thing more of note. When we joined the Khronos Group to further OpenCL development, some features needed to take advantage of an FPGA’s capabilities were lacking in the standard—characteristics like dataflow, for example. We were able to convince the standardization group to add these features. So we have been actively engaged in helping to mold the standards to provide more interesting capabilities.

 

I’m very excited about SDAccel, actually.

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About the Author
  • Be sure to join the Xilinx LinkedIn group to get an update for every new Xcell Daily post! ******************** Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.