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The Zynq PS/PL, Part One: Adam Taylor’s MicroZed Chronicles Part 21

by Xilinx Employee on ‎02-24-2014 09:48 AM (34,717 Views)

By Adam Taylor

 

So far in this epic series of blogs, we have looked at

 

  • Creating a Zynq-based system using the Vivado Design Suite
  • Configuration and boot loading
  • Using the XADC
  • Using the MIO and EMIO
  • The Zynq SoC’s interrupt structure
  • Zynq private timers and watchdogs
  • The Zynq SoC’s Triple Timer Counter

 

All of these functions are primarily focused upon the processing system (PS) side of the Zynq SoC. However, the really exciting aspect of the Zynq SoC from a design perspective is creating an application that uses the Zynq’s programmable logic (PL). Using the PL offloads tasks from the PS to the PL side, which accelerates the tasks and reclaims processor bandwidth for additional tasks. In addition, the PS side can control operations performed by the PL side in a classic system-on-chip application.

 

Using the Zynq SoC’s PL side can increase system performance, reduce power, and deliver predictable latency for real-time events. Those are all very good things for embedded systems designers.

 

The Zynq PS and PL are interconnected via the following interfaces:

 

  • Two 32-bit Master AXI ports (PS master)
  • Two 32-bit Slave AXI ports (PL Master)
  • Four 32/64-bit Slave High Performance Ports (PL Master)
  • One 64-bit Slave Accelerator Coherency Port (ACP) (PL Master)
  • Four clocks from the PS to the PL
  • PS to PL Interrupts
  • PL to PS Interrupts
  • DMA peripheral request interfaces

 

Here’s a block diagram illustrating these various interfave points:

 

 

Zynq PS-PL Interface Points.jpg

 

 

ARM’s AXI is a burst-orientated protocol intended for high bandwidth while providing low latency. Each AXI port contains independent read and write channels. One version of the AXI protocol that’s used by less demanding interfaces is AXI4-Lite, which is a simpler protocol that can be used for register-style control/status interfaces. For example, the Zynq XADC is connected to the Zynq PS using an AXI4-Lite interface.

 

More information on the AXI protocol can be found here http://www.arm.com/products/system-ip/amba/amba-open-specifications.php

 

The Zynq SoC supports three different AXI transfer types that you can use to interface the PS to the PL side of the device:

 

  • AXI4 Burst transfers
  • AXI4-Lite for simple control interfaces
  • AXI4-Streaming for unidirectional data transfers

 

The theoretical bandwidths of each of the interfaces are defined in the table below:

 

 

Maximum Zynq SoC PS-PL Transfer Rates.jpg

 

 

You must use the Zynq SoC’s DMA controller to achieve the maximum speeds listed in the table above. As an added benefit, the DMA controller reduces the load on the Zynq SoC’s ARM Cortex-A9 MPCore processors when the PS is the master. Without using the DMA controller, the maximum transfer rate from the PS to the PL side is 25Mbytes/sec.

 

All told, there is a phenomenal theoretical bandwidth of 14.4Gbytes/sec (115.2Gbits/sec) to be used between the PS and the PL! Over the next few blog posts, we will look more in detail at how we create and use peripherals within the PL side of the device to increase system performance. As engineers we are responsible for selecting the optimal interface to achieve the desired system performance using the most cost-effective approach.

 

 

Please see the previous entries in this MicroZed series by Adam Taylor:

 

Introduction to the Zynq Triple Timer Counter Part Four: Adam Taylor’s MicroZed Chronicles Part 20

 

Introduction to the Zynq Triple Timer Counter Part Three: Adam Taylor’s MicroZed Chronicles Part 19

 

Introduction to the Zynq Triple Timer Counter Part Two: Adam Taylor’s MicroZed Chronicles Part 18

 

Introduction to the Zynq Triple Timer Counter Part One: Adam Taylor’s MicroZed Chronicles Part 17

 

The Zynq SoC’s Private Watchdog: Adam Taylor’s MicroZed Chronicles Part 16

 

Implementing the Zynq SoC’s Private Timer: Adam Taylor’s MicroZed Chronicles Part 15

 

MicroZed Timers, Clocks and Watchdogs: Adam Taylor’s MicroZed Chronicles Part 14

 

More About MicroZed Interrupts: Adam Taylor’s MicroZed Chronicles Part 13

 

MicroZed Interrupts: Adam Taylor’s MicroZed Chronicles Part 12

 

Using the MicroZed Button for Input: Adam Taylor’s MicroZed Chronicles Part 11

 

Driving the Zynq SoC's GPIO: Adam Taylor’s MicroZed Chronicles Part 10

 

Meet the Zynq MIO: Adam Taylor’s MicroZed Chronicles Part 9

 

MicroZed XADC Software: Adam Taylor’s MicroZed Chronicles Part 8

 

Getting the XADC Running on the MicroZed: Adam Taylor’s MicroZed Chronicles Part 7

 

A Boot Loader for MicroZed. Adam Taylor’s MicroZed Chronicles, Part 6 

 

Figuring out the MicroZed Boot Loader – Adam Taylor’s MicroZed Chronicles, Part 5

 

Running your programs on the MicroZed – Adam Taylor’s MicroZed Chronicles, Part 4

 

Zynq and MicroZed say “Hello World”-- Adam Taylor’s MicroZed Chronicles, Part 3

 

Adam Taylor’s MicroZed Chronicles: Setting the SW Scene

 

Bringing up the Avnet MicroZed with Vivado

 

 

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About the Author
  • Be sure to join the Xilinx LinkedIn group to get an update for every new Xcell Daily post! ******************** Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.