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Using the SDSoC IDE for System-level HW-SW Optimization on the Zynq SoC

by Xilinx Employee ‎09-04-2015 01:57 PM - edited ‎09-04-2015 02:00 PM (20,658 Views)

 

By Daniele Bagni, Xilinx, Inc.

 

When Xilinx released the device in 2011, the Zynq SoC gained an instant following among a subset of embedded systems engineers and architects well versed in hardware design languages and methodologies as well as in embedded software development. The first-of-its-kind Zynq SoC today is deployed in embedded applications ranging from wireless infrastructure to smart factories and smart video/vision, and it is quickly becoming the de facto standard platform for advanced driver assistance systems. To make this remarkable device available to embedded engineers who have a strong software background but no HDL experience, Xilinx earlier this year introduced the Eclipse-based SDSoC integrated development environment, which enables software engineers to program the programmable logic as well as the ARM processing system of the Zynq SoC.

 

As shown in the figure below, the Zynq SoC consists of two major functional blocks: the PS (composed of the application processor unit, memory interfaces, peripherals and interconnect) and the PL (the traditional FPGA fabric).

 

 

Zynq High-Level Architectural View.jpg

 

The PS and PL are tightly coupled via interconnects compliant with the ARM AMBA AXI4 interface. Four high-performance (HP) AXI4 interface ports connect the PL to asynchronous FIFO interface blocks in the PS, thereby providing a high-throughput data path between the PL and the PS memory system (DDR SDRAM and on-chip memory). The AXI4 Accelerator Coherency Port (ACP) allows low-latency cache-coherent access to L1 and L2 cache directly from the PL masters. The General Purpose (GP) ports are accessible to both the PS and PL.

 

The latest Vivado Design Suite features made life a bit easier for design and development teams working with the Zynq SoC. But with a hardware-centric optimization workflow, not too much could be done to shorten the development time required to explore different data movers and PS-PL interfaces and to write and debug drivers and applications. If the whole system did not meet the design requirement in terms of throughput, latency or area, the team would have to revisit the hardware architecture by modifying the system connectivity and those modifications inevitably would lead to changes in the software. In some cases, a lack of acceleration or a hardware utilization overflow would force the team to revisit the original hardware-software partitioning. Multiple hardware and software teams would have to create another iteration of the system to explore other architectures that might meet the end requirement.

 

The SDSoC environment greatly simplifies the Zynq SoC development process, slashing total development time by largely automating the creation of IP blocks, the assembly of these IP blocks into a system-level design, and the creation of appropriate drivers and application code. The development environment generates the hardware and software components needed to synchronize hardware and software and to preserve original program semantics, while employing task-level parallelism, pipelined communication, and parallel computation to achieve high performance. The SDSoC environment automatically orchestrates all necessary Xilinx tools (Vivado, IP Integrator, HLS and SDK) to generate a full hardware-software system targeting the Zynq SoC—and does so with minimum user intervention.

 

Note: This blog post is an excerpt from an article appearing in the new Xcell Software Journal, which just went online. You can read the full article, which includes far more detail with an example, by downloading the PDF of this first issue here or clicking here to read the article online.

 

 

 

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About the Author
  • Be sure to join the Xilinx LinkedIn group to get an update for every new Xcell Daily post! ******************** Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.