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Vivado 2017.3 HLx Editions now ready to download. Here’s why you’ll want to upgrade immediately (if not sooner)

by Xilinx Employee on ‎10-11-2017 08:55 AM (4,077 Views)

 

The Vivado 2017.3 HLx Editions are now available and the Vivado 2017.3 Release Notes (UG973) tells you why you’ll want to download this latest version now. I’ve scanned UG973, watched the companion 20-minute Quick Take video, and cherry-picked twenty of the many enhancements that jumped out at me to help make your decision easier:

 

 

  • Reduced compilation time with a new incremental compilation capability

 

  • Improved heuristics to automatically choose between high-reuse and low-reuse modes for incremental compilation

 

  • Verification IP (VIP) now included as part of pre-compiled IP libraries including support for AXI-Stream VIP

 

  • Enhanced ability to integrate RTL designs into IP Integrator using drag-and-drop operations. No need to run packager any more.

 

  • Checks put in place to ensure that IP is available when invoking write_bd_tcl command

 

  • write_project_tcl command now includes Block designs if they are part of the project

 

  • Hard 100GE Subsystem awareness for the VCU118 UltraScale+ Board with added assistance support

 

  • Hard Interlaken Subsystem awareness for the VCU118 UltraScale+ Board with assistance support

 

  • Support added for ZCU106 and VCU118 production reference boards

 

  • FMC Support added to ZCU102 and ZCU106 reference boards

 

  • Bus skew reports (report_bus_skew) from static timing analysis now available in the Vivado IDE

 

  • Enhanced ease of use for debug over PCIe using XVC

 

  • Partial Reconfiguration (PR) flow support for all UltraScale+ devices in production

 

  • Support for optional flags (FIFO Almost Full, FIFO Almost Empty, Read Data Valid) in XPM FIFO

 

  • Support for different read and write widths while using Byte Write Enable in XPM Memory

 

  • New Avalon to AXI bridge IP

 

  • New USXGMII Subsystem that switches 10M/100M/1G/2.5G/5G/10G on 10GBASE-R 10G GT line rate for NBASE-T standard

 

  • New TSN (Time-Sensitive Network) subsystem

 

  • Simplified interface for DDR configuration in the Processing Systems Configuration Wizard

 

  • Fractional Clock support for DisplayPort Audio and Video to reduce BOM costs

 

 

 

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About the Author
  • Be sure to join the Xilinx LinkedIn group to get an update for every new Xcell Daily post! ******************** Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.