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Wild River Technology’s signal-integrity platforms and UltraScale+ FPGA GTY SerDes help characterize links at 32Gbps and up

by Xilinx Employee ‎03-09-2017 10:50 AM - edited ‎03-21-2017 07:46 AM (14,605 Views)

 

A LinkedIn blog published last month by Alfred P Neves of Wild River Technology describes a DesignCon 2017 tutorial titled “32 to 56Gbps Serial Link Analysis and Optimization Methods for Pathological Channels.” (You can get a copy of the paper here on the Wild River Web site. Registration required.) Co-authors of the turorial included Al Neves and Tim Wang Lee of Wild River Technology, Heidi Barnes and Mike Resso of Keysight, and Jack Carrel and Hong Ahn of Xilinx.

 

The tutorial discussed ways to test pathological channels at these nose-bleed serial speeds and those methods employed the bulletproof GTY SerDes on a Xilinx 16nm UltraScale+ FPGA for the 32Gbps transmitters and receivers as well as the Wild River ISI-32 loss platform and XTALK-32 crosstalk platform and Keysight test equipment.

 

Here’s a photo of the test setup showing the Xilinx UltraScale+ FPGA characterization board on the right, the Wild River test platforms on the left, and the Keysight test equipment in the background:

 

 

Wind River Technology ISI-32 Test Platform with UltraScale FPGA.jpg

 

 

If you don’t want to scan the DesignCon tutorial presentation, you can also watch a free 1-hour recorded Webinar about the topic on the Keysight web site. Click here.

 

Comments
by Visitor priffault
on ‎03-20-2017 04:47 PM

 

 

You might want to get the name of the company right.

 

The company you are talking about is Wild River Tech

 

Wind River does software products and is an Intel company

by Xilinx Employee
on ‎03-21-2017 11:47 AM

Thanks priffault, I claim temporary blindness. I've corrected the name as you suggested.

 

--Steve

 

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About the Author
  • Be sure to join the Xilinx LinkedIn group to get an update for every new Xcell Daily post! ******************** Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.