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Xilinx Reconfigurable Acceleration Stack speeds programming of machine learning, data analytics, video-streaming apps

by Xilinx Employee ‎11-14-2016 06:24 AM - edited ‎11-14-2016 01:54 PM (8,374 Views)


Today marks the launch of the Xilinx Reconfigurable Acceleration Stack for reducing the programming hurdles associated with accelerating workloads in hyperscale datacenters in three acceleration stack categories:


  • machine learning
  • data analytics
  • live-video streaming


Here’s a graphical overview of the material you’ll find in the Xilinx Reconfigurable Acceleration Stack:



Xilinx Acceleration Stack.jpg


The several libraries already included in the Xilinx Reconfigurable Acceleration Stack include:


DNN – A Deep Neural Network (DNN) library from Xilinx, which is a highly optimized library for building deep learning inference applications.  This library is designed for maximum compute efficiency at 16-bit and 8-bit integer data types.


GEMM – A General Matrix Multiply (GEMM) library from Xilinx, which is based on the level-3 Basic Linear Algebra Subprograms (BLAS). This library delivers optimized performance at 16-bit and 8-bit integer data types and supports matrices of any size.


HEVC Decoder & Encoder – HEVC/H.265 is the latest video-compression standard from the MPEG and ITU standards bodies. HEVC/H.265 is the successor to the H.264 video-compression standard and it can reduce video bandwidth requirements by as much as 50% relative to H.264. Xilinx provides two HEVC/H.265 video encoders: a high-quality, flexible, real-time encoder to address the majority of video-centric data-center workloads and an alternate encoder for non-camera generated content.  One decoder supports all forms of encoded HEVC/H.265 video from either encoder.


Data Mover (SQL) – The SQL data-mover library makes it easy to accelerate data analytics workloads using a Xilinx FPGA. The data-mover library orchestrates standard connections to SQL databases by sending blocks of data from database tables to the FPGA accelerator card’s on-chip memory over a PCIe interface. The library automatically maximizes PCIe bandwidth between the host CPU and the FPGA-based hardware accelerator.


Compute Kernel (SQL) – A library that accelerates numerous core SQL functions on the FPGA hardware accelerator including decimal type, date type, scan, compare, and filter. The library’s compute functions optimally exploit the on-board FPGa’s massive hardware parallelism.


Three of the top seven hyperscale cloud companies including Baidu have already deployed Xilinx FPGAs for hardware acceleration. Last month, Baidu announced that it had designed a Xilinx Kintex UltraScale FPGA into an accelerator card and was using pools of these cards to accelerate machine learning inference. Qualcomm and IBM have announced strategic collaborations with Xilinx for data-center acceleration and the IBM engagement already has already resulted in a storage and networking acceleration framework called CAPI SNAP that eases the creation of accelerated applications such as NoSQL using Xilinx FGPAs. (See last month’s Xcell Daily blog post “OpenPOWER’s CAPI SNAP Framework eases the task of developing high-performance, FPGA-based accelerators for data centers.”)


In addition, Xilinx has been leading an industry initiative toward the development of an intelligent, cache coherent interconnect called CCIX.  Xilinx along with AMD, ARM, Huawei, IBM, Mellanox, and Qualcomm formed the CCIX Consortium in May 2016. The initiative’s membership has since tripled in just five months and the CCIX Consortium announced the Release1 specification covering the physical, data-link, and protocol layers, which is now available to the consortium’s members. (See “CCIX Consortium develops Release1 of its fully cache-coherent interconnect specification, grows to 22 members.”)


There’s a new resource center on www.xilinx.com called the Xilinx Acceleration Zone that you can access for much more information about the new Xilinx Reconfigurable Acceleration Stack.


About the Author
  • Be sure to join the Xilinx LinkedIn group to get an update for every new Xcell Daily post! ******************** Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.