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Zynq UltraScale+ RFSoC: All the processing power of 64- and 32-bit ARM cores, programmable logic plus RF ADCs, DACs

by Xilinx Employee on ‎10-03-2017 09:20 AM (26,085 Views)

 

You say you want a revolution

Well, you know

We all want to change the world

 

--“Revolution” written by John Lennon and Paul McCartney

 

 

Today, Xilinx announced five new Zynq UltraScale+ RFSoC devices with all of the things you expect in a Xilinx Zynq UltraScale+ SoC—a 4-core APU with 64-bit ARM Cortex A-53 processor cores, a 2-core RPU with two 32-bit ARM Cortex-R5 processors, and ultra-fast UltraScale+ programmable logic—with revolutionary new additions: 12-bit, RF-class ADCs, 14-bit, RF-class DACs, and integrated SD-FEC (Soft Decision Forward Error Correction) cores.

 

Just in case you missed the plurals in that last sentence, it’s not one but multiple RF ADCs and DACs.

 

That means you can bring RF analog signals directly into these chips, process those signals using high-speed programmable logic along with thousands of DSP48E2 slices, and then output processed RF analog signals—using the same device to do everything. In addition, if you’re decoding and/or encoding data, two of the announced Zynq UltraScale+ RFSoC family members incorporate SD-FEC IP cores that support LDPC coding/decoding and Turbo decoding for applications including 5G wireless communications, backhaul, DOCSIS, and LTE. If you’re dealing with RF signals and high-speed communications, you know just how revolutionary these parts are.

 

For everyone else not accustomed to handling RF analog signals… well you’ll just have to take my word for it. These devices are revolutionary.

 

Here’s a conceptual block diagram of a Zynq UltraScale+ RFSoC:

 

 

 

RFSoC Block Diagram.jpg 

 

 

Here’s a table that shows you some of the resources available on the new Zynq UltraScale+ RFSoC devices:

 

 

RFSoC Product Table.jpg 

 

 

As you can see from the table, you can get as many as eight 12-bit, 4Gsamples/sec ADCs or sixteen 12-bit, 2Gsamples/sec ADCs on one device. You can also get eight or sixteen 14-bit, 6.4Gsamples/sec DACs on the same device. Two of the Zynq UltraScale+ RFSoCs also incorporate eight SD-FECs. In addition, there are plenty of logic cells, DSP slices, and RAM on these devices to build just about anything you can imagine. (With my instrumentation background, I can imagine new classes of DSOs and VSTs (Vector Signal Transceivers), for example.)

 

You get numerous benefits by basing your design on a Zynq UltraScale+ RFSoC device. The first and most obvious is real estate. Putting the ADCs, DACs, processors, programmable logic, DSPs, memory, and programmable I/O on one device saves a tremendous amount of board space and means you won’t be running high-speed traces across the pcb to hook all these blocks together.

 

Next, you save the complexity of dealing with high-speed converter interfaces like JESD204B/C. The analog converters are already interfaced to the processors and logic inside of the device. Done. Debugged. Finished.

 

You also save the power associated with those high-speed interfaces. That alone can amount to several watts of power savings. These benefits are reviewed in a new White Paper titled “All Programmable RF-Sampling Solutions.

 

There’s a device family overview here.

 

And just one more thing. Today’s announcement didn’t just announce the Zynq UltraScale+ RFSoC device family. The announcement headline included one more, very important word: “Delivers.”

 

 

As in shipped.

 

 

Because Xilinx doesn’t just announce parts. We deliver them too.

 

 

For more information about the Zynq UltraScale+ RFSoC device family, please contact your friendly neighborhood Xilinx sales representative or Avnet sales representative.

 

 

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About the Author
  • Be sure to join the Xilinx LinkedIn group to get an update for every new Xcell Daily post! ******************** Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.