Displaying articles for: 01-15-2017 - 01-21-2017
The IIC (Industrial Internet Consortium) announced its first security assessment-focused testbed for Industrial IoT (IIoT) systems, the Security Claims Evaluation Testbed, in February 2016. This testbed provides an open, highly configurable cybersecurity platform for evaluating the security capabilities of endpoints, gateways, and other networked components. Data sources to the testbed can include industrial, automotive, medical, and other related endpoints.
IIC member companies have developed a common security framework and an approach to assessing cybersecurity in IIoT systems: the Industrial Internet Security Framework (IISF). The IIC’s Security Claims Testbed helps manufacturers improve the security posture of their products and verify alignment to the IISF prior to product launch, which helps shorten time to market.
If you’d like to hear about these topics in more detail, the IIC is presenting a free 1-hour Webinar on January 26. (Available later, on demand.) Register here.
Here’s a graphic depicting the IIC’s Security Claims Evaluation Testbed:
Note: Xilinx is one of the lead member companies involved in the development of the IIC Security Claims Testbed—others include Aicas, GlobalSign, Infineon, Real-Time Innovations, and UL (Underwriters Laboratories)—and if you look at the above graphic, you’ll see the SoC-e Gateway in the middle of everything. This gateway is based on a Xilinx Zynq SoC. For more information about the SoC-e IIoT Gateway, see “Intelligent Gateways Make a Factory Smarter” and “Big Data Analytics + High Availability Network = IIoT: SoC-e demo at Embedded World 2016.”
Xilinx has a version of QEMU—a fast, open-source, just-in-time functional simulator—for the ARM processors in the Zynq SoC and the Zynq UltraScale+ MPSoC and for the company’s MicroBlaze soft processor core. QEMU accelerates code development by giving embedded software developers an enhanced execution environment long before hardware is available and they can continue to use QEMU as a software-development platform even after the hardware is ready. (After all, it’s a lot easier to distribute QEMU to 300 software developers than to ship hardware units to each of them.)
Although QEMU was already available through the open-source community, Xilinx has added several innovations over time to match the multi-core, heterogeneous devices available in the two distinct Zynq device families, augmented by additional MicroBlaze processors instantiated in programmable logic.
The latest version of Xilinx QEMU, available on github at https://github.com/Xilinx/qemu, includes extended features including:
Xilinx is actively developing QEMU enhancements, which means more features are on the way. Meanwhile, you’ll find the Xilinx QEMU Wiki here.
Introduced last month, VadaTech’s AMC596 places just a few chips on an AMC module—a Xilinx Virtex UltraScale VU440 FPGA, a QorIQ PPC2040 quad-core PowerPC processor, and 8Gbytes of DDR4 SDRAM—but you can build nearly anything with a combo like that. As the company says, this module is “ideal for ASIC prototyping/emulation” but it will also perform well in moderate-volume designs where the economics of ASIC design and manufacture do not deliver an advantage.
Here’s a photo of the AMC596 AMC module:
VadaTech AMC596 AMC Module
And here’s a block diagram:
VadaTech AMC596 AMC Module Block Diagram
The Xilinx Virtex UltraScale VU440 FPGA on the VadaTech AMC596 module is a DSP monster with 2880 DSP48E2 slices on chip along with 5541K system logic cells.
Despite the immense processing power built into VadaTech’s AMC596 module, it’s power consumption rating is only about 65W (depending on the application). In addition, the module measures a mere 73.5x180.6 mm. That’s a lot of capability packed into a small, low-power form factor.
Please contact VadaTech directly for additional information about the AMC596 module.
Edico Genome and Dell EMC have developed a bundled compute-and-storage solution for rapid, cost-effective and accurate analysis of next-generation bio-sequencing data. The bundle consists of Edico Genome’s DRAGEN processor integrated into a 1U Dell 4130 server with Dell EMC’s Isilon scale-out networked attached storage (NAS). Edico Genome’s DRAGEN bio-IT processor is designed to analyze sequencing data quickly using the hardware acceleration of a Xilinx FPGA. (For more information about the Edico Genome DRAGEN processor, see “FPGA-based Edico Genome Dragen Accelerator Card for IBM OpenPOWER Server Speeds Exome/Genome Analysis by 60x.”)
For more information about this Edico/Dell bio-processor bundle, click here.
Next Platform Press has just published a revised version of last year’s “FPGA Frontiers: New Applications in Reconfigurable Computing, 2017 Edition,” an 87-page book by Nicole Hemsoth and Timothy Prickett Morgan—co-editors of www.nextplatform.com, a Web site dedicated to “in-depth coverage of high-end computing at large enterprises, supercomputing centers, hyperscale data centers, and public clouds.”
Although it’s not a Xilinx-specific book (or even a Xilinx-centric book), we at Xilinx would like to get a copy of this comprehensive book into your hands if you’re interested in the use of FPGAs in data centers and cloud computing. FPGA Frontiers: New Applications in Reconfigurable Computing covers the topic from the objective perspective .
As Xilinx CTO Ivo Bolsen’s writes in his intro to the 2017 edition of this book, “the broader compute world has an opportunity with FPGAs as well given larger trends in the datacenter, most notably performance per watt and overall scalability. Scaling up and down at the same time as having programmability mean more in the wake of these trends, and this of course maps well to FPGAs.”
From now until January 27, you can download a free PDF of the book, courtesy of Xilinx, by clicking here.
Three years ago, Opal Kelly introduced an enhanced version of its XEM6310 USB 3.0 FPGA module based on the Xilinx Spartan-6 FPGA family. (See “Need a fast way to develop complex, real-time USB 3.0 peripheral devices? This 60x75mm FPGA-based module can help.”) Now, the company has revamped the product using Xilinx Artix-7 FPGAs to create the XEM7310 USB 3.0 integration module.
Opal Kelly’s new XEM7310 USB 3.0 Integration Module is based on the Xilinx Artix-7 FPGA family
It has the same, diminutive 50x75mm footprint and the same set of dual 80-pin high-density connectors on the bottom, but the silicon resources on the board have been seriously upgraded.
First, the two available Artix-7 FPGAs on the XEM7310 board (Artix-7 A75 or A200 devices) provide significantly more programmable-logic resources than the Spartan-6 devices available on the older XEM6310. Here’s a chart showing what the XEM7310 provides:
Next, the XEM7310 board incorporates eight times as much SDRAM (1Gbyte of DDR3 SDRAM versus 128Mbytes of DDR2 SDRAM).
The XEM7310 board’s system clock is 200MHz rather than 100MHz for the older product.
One thing’s similar: the new board has complete APIs in C, C++, C#, Ruby, Python, and Java like the earlier XEM6310.
The XEM7310-A75 sells for $549.95 and the XEM7310-A200 sells for $799.95, in unit quantities.
If you need a capable, ready-made PXIe control module, take a look at the just-announced COPious-PXIe embedded module from Innovative Intgration. The module is based on a Xilinx Zynq Z-7045 SoC, which means it has a dual-core ARM Cortex-A9 MPCore processor and a very large chunk of Xilinx programmable logic. One of the ARM processors on the COPious-PXIe embedded module can be tasked to run Linux while the other can run an RTOS in conjunction with Linux. The module has 1Gbyte of on-board DDR3 SDRAM to hold code and data for the ARM processors.
In addition to the dual-core ARM Cortex-A9 MPCore processor, the Zynq Z-7045 SoC includes 350K programmable logic cells, 19.1Mbits of BRAM, and 900 DSP48E1 DSP slices. You can build a ton of customized processing power with those on-chip components using Xilinx Vivado tools.
The COPious-PXIe embedded module module also has an HPC FMC connector with front-panel access for adding a variety of high-performance FMC modules, which permit extensive hardware customization using a variety of off-the-shelf components with I/O capabilities that include high-speed ADCs and DACs, QSFP+ or SFP+ optical networking ports, or 10G Ethernet ports.
Here’s a block diagram of the module:
COPious-PXIe Embedded Module Block Diagram
The SpaceX Falcon 9 rocket put the first ten Iridium NEXT global comms satellites into LEO (low-earth orbit) last Saturday from Space Launch Complex 4E at Vandenberg Air Force Base in California. (Iridium orbits are 476 miles or 780km above the earth.) Iridium partnered with Thales Alenia Space for the manufacturing, assembly, and testing of 81 Iridium NEXT satellites. Ultimately, there will be 66 cross-linked satellites in the Iridium NEXT constellation—with spares, there will be more than 70 satellites in orbit—which will provide global point-to-point communications over every square inch of the earth’s surface.
These new satellites will dramatically increase the Iridium network’s bandwidth. Iridium Certus, the next-generation multi-service communications platform enabled by Iridium NEXT, will deliver faster speeds and higher throughputs across multiple industry verticals including maritime, aviation, land mobile, M2M, and government comms markets.
Each of the ten Iridium NEXT satellites in this launch incorporates several Xilinx space-grade Virtex-5QV FPGAs used to implement the satellites’ On Board Processor (OBP) hardware developed by SEAKR Engineering. (Space-grade Virtex-5QV FPGAs are the radiation-hardened version of commercial Xilinx Virtex-5 FPGAs and were developed under sponsorship by AFRL's Space Vehicles Directorate.)
Here’s a short video describing the new Iridium NEXT constellation:
Why boost FPGAs into a space-based comms application? “The re-configurability of Xilinx’s space-grade Virtex-5QV FPGA enables Iridium NEXT to continue in-orbit integration of future advancements and innovations throughout its operational lifetime, providing scalability and flexibility for potential new applications not yet envisioned,” said Eric Anderson, president at SEAKR Engineering.
Here’s a 3-minute video clip of Saturday’s SpaceX launch of the Falcon 9 rocket carrying the Iridium NEXT satellites into LEO:
And just because it’s really, really cool, here’s a short clip of the Falcon 9 rocket’s first-stage re-entry and its successful tail-first landing on its drone ship “Just Read the Directions” in the Pacific Ocean:
Need a really powerful SOM (system on module) with six heterogeneous ARM processor cores (four 64-bit ARM Cortex-A53 cores and two 32-bit ARM Cortex-R5 cores), an ARM Mali-400 MP2 GPU, and a big chunk of the latest-generation UltraScale+ programmable logic? Sounds like you need the Avnet-designed UltraZed-EG SOM based on a Xilinx Zynq UltraScale+ MPSoC (XCZU3EG). This $599 board is tiny (2x3.5 inches) but packs a wallop in the form of the Zynq UltraScale+ MPSoC, 2Gbytes of DDR4 SDRAM, and a bunch of I/O ports. That’s a ton of processing power for projects that require heavy lifting.
Here’s a photo of the SOM:
$599 Avnet UltraZed-EG SOM
And here’s a block diagram of the SOM to give you a better idea of what’s on the SOM.
Avnet UltraZed-EG SOM Block diagram
Pentek’s new video discusses the broad product line of more than 20 Jade XMC, PCIe, AMC, compact PCI, and VPX boards based on the Xilinx Kintex UltraScale FPGA family. The Pentek Jade modules are designed for high-performance data-acquisition and signal-processing applications with on-board ADCs and DACs as fast as 5G samples/sec.
The broad Jade product line illustrates how a company can take a basic idea and use programmable logic to develop comprehensive, multi-member product lines while minimizing engineering effort by leveraging the numerous resources included in the broad line of mutually compatible Xilinx Kintex UltraScale FPGAs. The Jade family represents the latest generation of related products that Pentek has based on three successive generations of Xilinx FPGAs. This latest generation from Pentek is 13% lighter, uses 23% less power, and costs about 30% less than the preceding generation, partly due to using next-generation Xilinx devices.
The Jade product line illustrates this concept especially because Pentek has not only developed a comprehensive line of board-level products, the company has also created a set of support tools called Navigator Design Suite that provides BSPs and software support for the Jade modules using Pentek-supplied IP for the on-board FPGAs. A companion tool called the Navigator FPGA Design Kit allows you to develop your own IP for high-speed data acquisition and signal processing. The Navigator BSP package and the Navigator FPGA Design Kit are closely linked so that the software and hardware IP dovetail.
Here’s the 4-minute Pentek video:
Note: For additional information on the Pentek Jade product line, see “Pentek kicks its radar, SDR DSP architecture up a notch from Cobalt to Onyx to Jade by jumping to Kintex UltraScale FPGAs.”
By Adam Taylor
Having looked that how we can optimize the Zynq SoC’s PS (processor system) for power during operation and when we wish for the Zynq SoC to enter sleep mode, I now want to round off our look at power-reduction techniques by looking at how we reduce power consumption within the Zynq SoC’s PL (programmable logic) using design techniques. Obviously, one of the first things we should do is enable power optimization within implementation flow, which optimizes the design for power efficiency. However, Vivado tools can only optimize a design as presented. So let’s see what we can do to ensure that we present the best design possible.
Setting Power Optimization within Vivado
One of the first places to start is to ensure that we are familiar with the structure of the CLBs and slices used to implement our creations within the Zynq SoC’s PL. If you are not as familiar as you should be, the detail of these PL components is provided within in the Seven Series CLB user guide UG474.
Each CLB contains two slices. These slices provide the LUTs (look up tables), storage elements, etc. used to implement the logic in your design. The first thing we can do to optimize power consumption in our programmable logic design is to consider the polarity, synchronicity, and grouping of control signals to these CLB’s and slices. When we talk about a control signal, we mean the clock, clock enable, set/reset, and distributed-RAM write enables used within a slice.
Storage elements in a Programmable Logic Slice
Looking at the storage elements shown above, you can see that except for the CLK control signal, which has a mux to enable its inversion, all other signals are active high. If we declare them as active low or asynchronous, we will require an extra LUT to invert the signal and additional routing resources to connect the inverter. These extra logic and routing resources increase power consumption.
Grouping of control signals relates to how a specific group of control signals—e.g. the clock, reset and clock enable—behave. Creating many different control groups within a design or module makes it more difficult for the placer to locate elements within different control groups close together. The end result will require more routing which makes timing closure more difficult and increases power consumption.
We also need to consider how we use and configure the PL’s I/O resources. For instance, we must giver proper consideration to limiting drive strength and slew rate. We should also consider using the lowest I/O voltage supported by the receiving device. For example, can we may be able to use reduced-swing LVDS in place of LVDS.
More advanced design techniques that we can use relate to the use of hard macros within the PL and how the tools use this logic. One of the biggest savings can be achieved by using a smaller device, which clearly reduces overall power. There are two main techniques we can use to reduce the size of the required device. The first of these is resource time sharing, which uses the same on-chip logic resources for different functions at different times. A second approach is to use a common core for processing multiple inputs and inputs if possible. However, this technique increases complexity during design capture because we must consider multiplexing and sequencing needs.
Once we have completed our design, we can run the XPE tool within Vivado to estimate power consumption and predict junction temperature (very important!). Hopefully, we’ll get the reduction power we require. However, if we do not, we can perform “what if” scenarios as detailed by UG907, which also contains other low-power design techniques.
Code is available on Github as always.
If you want E book or hardback versions of previous MicroZed chronicle blogs, you can get them below.
All of Adam Taylor’s MicroZed Chronicles are cataloged here.