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An article in the new January, 2017 issue of the IIC (Industrial Internet Consortium’s) Journal of Innovation titled “Making Factories Smarter Through Machine Learning” discusses the networked use of SoC-e’s CPPS-Gate40 intelligent IIoT gateway to help a car-parts manufacturer keep the CNC machines on its production lines up and running through predictive maintenance directed by machine-learning algorithms. These algorithms use real-time operational data taken directly from sensors on the CNC machines to identify and learn normal behavior patterns during the machining process so that when variances signaling an imminent failure occur, systems can be shut down gracefully and maintained or repaired before the failure becomes truly catastrophic (and really, really expensive thanks to any uncontrolled release of the kinetic energy stored as angular momentum in an operating CNC machine).
Catastrophic CNC machine failures can shut down a production line, causing losses worth hundreds of thousands of dollars (or more) in physical damage to tools and to work in process, in addition to the costs associated with lost production time. In one example cited in the article, a bearing in a CNC machine started to fail, as indicated by a large vibration spike. At that point, only the bearing needed replacement. Four days later, the bearing failed catastrophically damaging nearby parts and idling the production line for three shifts. There was plenty of warning (see image below) and preventative maintenance at the first indication of a problem would have minimized the cost of this single failed bearing.
Unfortunately, the data predicting the failure had been captured but not analyzed until afterwards because there was no real-time data collection-and-analysis system in place. What a needless waste.
The network based on SoC-e’s CPPS-Gate40 intelligent IIoT gateway discussed in this IIC Journal of Innovation article is designed to collect and analyze real-time operational information from the CNC machines including operating temperature and vibration data. This system performs significant data reduction at the gateway to minimize the amount of data feeding the machine-learning algorithms. For example, FFT processing shrinks the time-domain vibration data down to just a frequency and an amplitude, resulting in significant local data reduction. Temperature data varies more slowly and so it is sampled at a much lower frequency—variable-rate collection and fusion for different sensor data is another significant feature of this system. The full system then trains on the data collected by the networked IIoT gateways.
This is a simple and graphic example of the sort of return that companies can expect from properly implemented IIoT systems with the performance needed to operate real-time manufacturing systems.
SoC-e’s CPPS-Gate40 is based on a Xilinx Zynq SoC, which implements a variety of IIoT-specific, hard-real-time functions developed by SoC-e as IP cores for the Zynq SoC's programmable logic including the HSR/PRP/Ethernet switch (HPS), IEEE 1588-2008 Precision Time Protocol (see “IEEE 1588-2008 clock synchronization IP core for Zynq SoCs has sub-μsec resolution”), and real-time sensor data acquisition and fusion. SoC-e also uses the Zynq SoC to implement a variety of network security protocols. These are the sort of functions that require the flexibility of the Zynq SoC’s integrated programmable logic. Software-based implementations of these functions are simply impractical due to performance requirements.
bysleibso01-26-201710:41 AM - edited 01-27-201709:16 AM
TI has created a power supply reference design for the Xilinx Zynq UltraScale+ MPSoC specifically for Remote Radio Head (RRH) and backhaul applications but there’s no reason you can’t use this design in any other design employing the Zynq UltraScale+ MPSoC. The compact reference design is based on TI’s TPS6508640 power-management IC (PMIC), which is a pretty sophisticated power supply controller, several power FETs, and a TPS544C25 high-current regulator. The TPS6508640 PMIC reduces board size, cost, and power loss using a high switching frequency and separate rails for core supplies.
The design creates ten regulated supply voltages for the Zynq UltraScale+ MPSoC based on a 12V source supply. Here’s what TI’s reference design looks like:
Here’s what the design looks like when placed on a pc board:
You’ll find a PDF describing this reference design in detail here.
Please contact TI directly for additional details.
An Industrial Ethernet (IIoT) power supply reference design for the Xilinx Zynq-7000 SoC developed by Monolithic Power Systems (MPS) combines small footprint (0.45in2 of board real estate) with good efficiency (78% from a 12V input) and tight regulation. The design consists of six MPS regulators: three MPM3630 3A buck regulators, one MPM3610 1A buck regulator, and two LDO regulators to supply the twelve power rails needed by the Zynq SoC.
Here’s a simple block diagram of MPS’ reference design:
IIoT power supply reference design for the Zynq SoC from Monolithic Power Systems
And here’s a close-up photo of MPS’ compact IIoT power supply design prototype:
For more information about the MPS power supply reference including a BOM and data sheets for the various regulators used in the design, click here.
The 4-minute video below demonstrates a real-time, dense optical flow demonstration running on a Xilinx Zynq SoC. The entire demo was developed using C/C++, the Xilinx SDSoC development environment, and associated OpenCV libraries. The dense optical flow algorithm compares successive video images to estimate the apparent motion of each pixel in the one of the images. This technique is used in video compression, object detection, object tracking, and image segmentation. Dense optical flow is a computationally-intensive operation, which makes it an ideal candidate for hardware acceleration using the programmable logic in a small, low-power Zynq SoC.
As Xilinx Senior Product Manager for SDSoC and Embedded Vision Nick Ni explains, SDSoC lowers the barriers to using the Zynq SoC in these embedded-vision applications because the tool makes it relatively easy for software developers accustomed to using only C or C++ to develop hardware-accelerated applications with the coding tools and styles they already know. SDSoC then converts the code that requires acceleration into hardware and automatically links this hardware to the software through DMA.
bysleibso01-25-201711:01 AM - edited 01-25-201711:51 AM
The short video below captured at the recent SDS Drives show in Germany shows two recent safety-related certifications for Xilinx development tools. The first is a TÜV SÜD certification for the Vivado Design Suite for functional-safety applications and the second is for the Xilinx MicroBlaze processor GNU compiler tool chain, certified to SIL 4.
The video also shows a Zynq SoC being used to implements a functional-safety application using two different processor architectures—an ARM Cortex-A9 and a Xilinx MicroBlaze soft processor core—running the same code. This demonstration shows the functional-safety flexibility you get when you design a Zynq SoC into your design.
bysleibso01-24-201709:50 AM - edited 01-24-201711:17 AM
Late last year at the SPS Drives show in Germany, BE.services demonstrated a vertically integrated solution stack for industrial controls running on a Zynq-based Xilinx ZC702 Eval Kit. The BE.services industrial automation stack for Industry 4.0 and IIoT applications includes:
Linux plus OSADL real-time extensions
POWERLINK real-time, industrial Ethernet
Matrikon OPC UA machine-to-machine protocol for industrial automation
Ethernet TSN (time-sensitive networking) with hardware IP support from Xilinx
This stack delivers the four critical elements you need when developing smart manufacturing controllers:
Here’s a 3-minute demo of that system with explanations:
The fundamental advantage to using a Xilinx Zynq SoC with its on-chip FPGA array for this sort of application is deterministic response, explains Dimitri Philippe in the video. Philippe is the founder and CEO of BE.services. Programmable logic delivers this response with hardware-level latencies instead of software latencies that are orders of magnitude slower.
Note: You can watch a recent Xilinx Webinar on the use of OPC UA and TSN for IIoT applications by clicking here.
Targeting military and other high-end, real-time computing applications, the PanaTeQ VPX3-ZU1 3U OpenVPX Module delivers the Xilinx Zynq UltraScale+ MPSoC with its six ARM processor cores (a quad-core ARM Cortex-A53 Application Processing Unit and a dual-core ARM Cortex-R5 Real-Time Processing Unit), an ARM MALI-400 Graphic Processing Unit, and big chunk of Xilinx’s advanced 16nm programmable logic available in the 100x160mm VPX form factor. The module also includes an on-board PCIe Gen2 switch driving eight PCIe ports on the VPX P1 port and an FMC site that complies with the Vita 57.1 HPC standard, which makes the VPX3-ZU1 board instantly compatible with a large number add-on I/O modules including the FMC-ZU1RF-A FMC Wideband RF Transceiver module based on the Analog Devices AD9371 Integrated, Dual RF Transceiver with Observation Path.
The VPX-ZU1 is available with one of three Xilinx Zynq UltraScale+ MPSoC devices (ZU6EG/ZU9EG/ZU15EG), and with either 2 or 4Gbytes of 64-bit DDR4-2400 SDRAM with 8-bit ECC for the Zynq UltraScale+ MPSoC’s processor system and either 512Mbytes or 1Gbyte of DDR4-2400 SDRAM connected to the Zynq UltraScale+ MPSoC’s programmable logic.
Here’s a detailed block diagram of the PanaTeQ VPX3-ZU1 3U OpenVPX Module:
bysleibso01-23-201709:51 AM - edited 01-30-201708:56 AM
By Adam Taylor
Many embedded systems are required to generate PWM (pulse-width modulated) signals, so I thought it would be a good idea to explain how you can do this using the Zynq SoC. I am going to show how to interface with a servomotor as a real-world example. Servomotors are used in applications such as robotics and advanced manufacturing. The way we interface with different servomotors varies depending on use, type, and cost. A servomotor interface can be either digital—in the form of a CAN or Modbus connection—or analog—like a PWM signal as mentioned above.
For this example, we are going to interface to a simple RC servo, which uses an analog PWM signal to drive the motor’s position. We can generate PWM signals directly from the Zynq SoC’s PS (processor system) using the Zynq SoC’s TTC (Triple Timer Counter).
Reviewing the TTC’s architecture, you will see that each of the three timers can generate a Wave-Out. For the first TTC, Wave-Out can be output either via the MIO or EMIO pins on the Zynq SoC, but the remaining two counters can only output this signal via EMIO.
For this example, we will be using the MicroZed board mounted on an I/O Carrier Card with the servos connected to one of the carrier card’s PMOD ports. Therefore, I will use the EMIO pins for all 6 TTC wave outputs. This means that we can drive up to 6 servos. In this example, I will use only two servos. Two servos allow me to demonstrate that I can use the software to ensure that the servos do not conflict with each other. Scaling up from two servos to six, or any number in between is then very straightforward.
As always, the first thing we need to do is create a hardware design within Vivado. After three years of the MicroZed Chronicles, you should be very familiar with this process. Create a new project in Vivado and add a block diagram with the Zynq Processing System contained within. With this added, we can quickly and easily set up the two available TTCs and enable the wave outs to be routed via the EMIO. It is then a simple case of directing these wave outputs to the Zynq PL’s I/O using a constraints file.
Enabling the TTC’s and directing them to EMIO
A very simple Zynq system for driving the Servo
With the bit file generated and exported for use in SDK, all we need to do now is understand how to drive the servo. We know it will use the PWM output for control, but we don’t know the specifics. The interface with the servo is very simple. There are three wires connected to most RC servos, two of these are power and ground while the third is the control wire uses to command the servo’s position. We use this wire to drive the motor to a position between -90 and +90 degrees, with 0 degrees being the neutral position. We command the servo to change its position by generating a PWM signal with a 20msec period between pulses. The pulse’s duty cycle is very low, varying from 2.5% to 12.5%. If we wish the servo to remain in the neutral position of 0 degrees, we must generate a 1.5msec pulse every 20msec. Moving to either extreme of +/-90 degrees is possible by either adding or subtracting 1msec to the pulse width used to achieve the neutral position.
In the next blog we will look at the software we need to generate this interface.
Director of Strategic Marketing and Business Planning
Be sure to join the Xilinx LinkedIn group to get an update for every new Xcell Daily post! ******************** Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.