Displaying articles for: 02-19-2017 - 02-25-2017
The six new PXI digitizers and AWGs (arbitrary waveform generators) in the Keysight M3xxx instrument series all take advantage of the real-time processing power and immense programmability of Xilinx Kintex-7 FPGAs. All six instruments are offered with either a Kintex-7 325T or 410T FPGA. Keysight provides programming libraries for C, C++, Visual Studio, LabVIEW, MATLAB, Python, other programming languages, and the Keysight M3602A Graphical FPGA Development Environment. Thanks to the built-in FPGA programmability, you can customize these instruments’ high- and low-level design elements using off-the-shelf DSP blocks, MATLAB/Simulink, the Xilinx CORE Generator and IP cores, and the Xilinx Vivado Design Suite with either VHDL or Verilog code. Clearly, Keysight has made FPGA programmability (and dynamic reprogrammability) integral to the feature sets of these instruments.
The six new Keysight PXI instruments are:
M3100A 100MSamples/sec, 4 or 8-channel FPGA digitizer
M3102A 500Msamples/sec, 2 or 4-channel FPGA digitizer
M3201A 500MSamples/sec FPGA arbitrary waveform generator
M3202A 1GSamples/sec FPGA arbitrary waveform generator
M3300A 500MSamples/sec, 2-channel FPGA AWG/digitizer combo
M3302A 500MSamples/sec, 4-channel FPGA AWG/digitizer combo
Keysight M3302A PXI AWG and Digitizer
According to a just-published article by Martin Rowe on EDN.com:
“The FPGA-based instruments in the table come from Signadyne, acquired by Keysight in 2016. The addition of the FPGA gives digitizers the ability to perform data processing on board, relieving the system controller from that resource-intensive task… Adding an FPGA to a waveform generator lets you program waveforms with complex modulation for emulating wireless signals such as [for] multiple input multiple output (MIMO) [antennas].”
This family of Keysight M3xxx instruments clearly demonstrates the ability to create an FPGA-based hardware platform that enables rapid development of many end products from one master set of hardware designs. In this case, the same data-acquisition and AWG block diagrams recur on the data sheets of these instruments, so you know there’s a common set of designs.
Xilinx FPGAs are inherently well-suited to this type of platform-based product design because of the All-Programmable (I/O, hardware, and software) nature of the devices. I/O programmability permits any-to-any connectivity—as is common with, for example, camera designs when you’re concerned about adapting to a range of sensors or different ADCs and DACs for digitizers and AWGs. Hardware programmability allows you to rapidly modify real-time signal-processing or motor-control algorithms—as is common with diverse designs including high-speed instrument designs and industrial controllers. Software programmability is of course pervasive and is common to every embedded design. Remember, all Xilinx devices give you all three; conventional SoCs, application processors, and microcontrollers do not.
With a month left in the Indiegogo funding period, the MATRIX Voice open-source voice platform campaign stands at 289% of its modest $5000 funding goal. MATRIX Voice is the third crowdfunding project by MATRIX Labs, based on Miami, Florida. The MATRIX Voice platform is a 3.14-inch circular circuit board capable of continuous voice recognition and compatible with the latest voice-based, cognitive cloud-based services including Microsoft Cognitive Service, Amazon Alexa Voice Service, Google Speech API, Wit.ai, and Houndify. The MATRIX Voice board, based on a Xilinx Spartan-6 LX4 FPGA, is designed to plug directly onto a low-cost Raspberry Pi single-board computer or it can be operated as a standalone board. You can get one of these boards, due to be shipped in May, for as little as $45—if you’re quick. (Already, 61 of the 230 early-bird special-price boards are pledged.)
Here’s a photo of the MATRIX Voice board:
This image of the top of the MATRIX Voice board shows the locations for the seven rear-mounted MEMS microphones, seven RGB LEDs, and the Spartan-6 FPGA. The bottom of the board includes a 64Mbit SDRAM and a connector for the Raspberry Pi board.
Because this is the latest in a series of developer boards from MATRIX Labs (see last year’s project: “$99 FPGA-based Vision and Sensor Hub Dev Board for Raspberry Pi on Indiegogo—but only for the next two days!”), there’s already a sophisticated, layered software stack for the MATRIX Voice platform that include a HAL (Hardware Abstraction Layer) with the FPGA code and C++ library, an intermediate layer with a streaming interface for the sensors and vision libraries (for the Raspberry Pi camera), and a top layer with the MATRIX OS and high-level APIs. Here’s a diagram of the software stack:
And now, who better to describe this project than the originators:
National Instruments (NI) has just added two members to its growing family of USRP RIO SDRs (software-defined radios)—the USRP-2944 and USRP-2945—with the widest frequency ranges, highest bandwidth, and best RF performance in the family. The USRP-2945 features a two-stage superheterodyne architecture that achieves superior selectivity and sensitivity required for applications such as spectrum analysis and monitoring, and signals intelligence. With four receiver channels, and the capability to share local oscillators, this SDR also sets new industry price/performance benchmarks for direction-finding applications. The USRP-2944 is a 2x2 MIMO-capable SDR that features 160MHz of bandwidth per channel and a frequency range of 10 MHz to 6 GHz. This SDR operates in bands well suited to LTE and WiFi research and exploration.
NI USRP RIO Platform
Like all of its USRP RIO products, the NI USRP-2944 and USRP-2945 incorporate Xilinx Kintex-7 FPGAs for local, real-time signal processing. The Kintex-7 FPGA implements a reconfigurable LabVIEW FPGA target that incorporates DSP48 coprocessing for high-rate, low-latency applications. With the company’s LabVIEW unified design flow, researchers can create prototype designs faster and significantly shorten the time needed to achieve results.
Here’s a block diagram showing the NI USRP RIO SDR architecture:
USRP RIO Block Diagram
Adam Taylor just published an EETimes review of the Xilinx RFSoC, announced earlier this week. (See “Game-Changing RFSoCs from Xilinx”.) Taylor has a lot of experience with high-speed analog converters: he’s designed systems based on them—so his perspective is that of a system designer who has used these types of devices and knows where the potholes are—and he’s worked for a semiconductor company that made them—so he should know what to look for with a deep, device-level perspective.
Here’s the capsulized summary of his comments in EETimes:
“The ADCs are sampled at 4 Gsps (gigasamples per second), while the DACs are sampled at 6.4 Gsps, all of which provides the ability to work across a very wide frequency range. The main benefit of this, of course, is a much simpler RF front end, which reduces not only PCB footprint and the BOM cost but -- more crucially -- the development time taken to implement a new system.”
“…these devices offer many advantages beyond the simpler RF front end and reduced system power that comes from such a tightly-coupled solution.”
“These devices also bring with them a simpler clocking scheme, both at the device-level and the system-level, ensuring clock distribution while maintaining low phase noise / jitter between the reference clock and the ADCs and DACs, which can be a significant challenge.”
“These RFSoCs will also simplify the PCB layout and stack, removing the need for careful segregation of high-speed digital signals from the very sensitive RF front-end.”
“I, for one, am very excited to learn more about RFSoCs and I cannot wait to get my hands on one.”
For more information about the new Xilinx RFSoC, see “Xilinx announces RFSoC with 4Gsamples/sec ADCs and 6.4Gsamples/sec DACs for 5G, other apps. When we say ‘All Programmable,’ we mean it!” and “The New All Programmable RFSoC—and now the video.”
Adam Taylor has published nearly 200 blogs in Xcell Daily but he’s reserved some of his best advice for embedded.com. Yesterday, he published a short article titled: “How to prevent FPGA-based projects from going astray.” In this article, Taylor describes five common issues that lead design teams astray:
Learn from the best. Spend five minutes and read Adam’s new article.
If you’re still uncertain as to what System View’s Visual System Integrator hardware/software co-development tool for Xilinx FPGAs and Zynq SoCs does, the following 3-minute video should make it crystal clear. Visual System Integrator extends the Xilinx Vivado Design Suite and makes it a system-design tool for a wide variety of embedded systems based on Xilinx devices.
This short video demonstrates System View’s tool being used for a Zynq-controlled robotic arm:
For more information about System View’s Visual System Integrator hardware/software co-development tool, see:
Avnet’s new $499 UltraZed PCIe I/O carrier card for its UltraZed-EG SoM (System on Module)—based on the Xilinx Zynq UltraScale+ MPSoC—gives you easy access to the SoM’s 180 user I/O pins, 26 MIO pins from the Zynq MPSoC’s MIO, and 4 GTR transceivers from the Zynq MPSoC’s PS (Processor System) through the PCIe x1 edge connector; two Digilent PMOD connectors; an FMC LPC connector; USB and microUSB, SATA, DisplayPort, and RJ45 connectors; an LVDS touch-panel interface; a SYSMON header; pushbutton switches; and LEDs.
$499 UltraZed PCIe I/O Carrier Card for the UltraZed-EG SoM
That’s a lot of connectivity to track in your head, so here’s a block diagram of the UltraZed PCIe I/O carrier card:
UltraZed PCIe I/O Carrier Card Block Diagram
For information on the Avnet UltraZed SOM, see “Look! Up in the sky! Is it a board? Is it a kit? It’s… UltraZed! The Zynq UltraScale+ MPSoC Starter Kit from Avnet” and “Avnet UltraZed-EG SOM based on 16nm Zynq UltraScale+ MPSoC: $599.” Also, see Adam Taylor’s MicroZed Chronicles about the UltraZed:
Yesterday, Xilinx announced breakthrough RF converter technology that allows the creation of an RFSoC with multi-Gsamples/sec DACs and ADCs on the same piece of TSMC 16nm FinFET silicon as the digital programmable-logic circuitry, the microprocessors, and the digital I/O. This capability transforms the Zynq UltraScale+ MPSoC into an RFSoC that's ideal for implementing 5G and other advanced RF system designs. (See “Xilinx announces RFSoC with 4Gsamples/sec ADCs and 6.4Gsamples/sec DACs for 5G, other apps. When we say ‘All Programmable,’ we mean it!” for more information about that announcement.)
Today there’s a 4-minute video with Sr. Staff Technical Marketing Engineer Anthony Collins providing more details including an actual look at the performance of a 16nm test chip with the 12-bit, 4Gsamples/sec ADC and the 14-bit, 6.4Gsamples/sec DAC in operation.
Here’s the video:
To learn more about the All Programmable RFSoC architecture, click here or contact your friendly, neighborhood Xilinx sales representative.
By Adam Taylor
A few weeks ago we looked at how we can generate PWM signals using the Zynq SoC’s TTC (Triple Time Counter). PWM is very useful for interfacing with motor drives and for communications. What we did not look at however was how we can measure the PWM signals received by the Zynq SoC.
The Zynq SoC’s TTC (Triple Timer Counter)
We can do this using the TTC’s event counters These 16-bit counters are clocked by CPU_1x and are capable of measuring the time an input signal spends high or low. This input signal can come from either MIO or EMIO pins for the first TTC in both TTC 0 and 1 or from EMIO pins in the reaming two timers in each of the TTCs.
The event timer is very simple to use, once you enable and configure it to measure either the high or low duration of the pulse. The time updates the event count regsiter once the high or low level it has been configured to measure completes.
With a 133MHz CPU_1x clock, this 16-bit register can measure events as long as 492 microseconds before it overflows.
If the event counter does overflow and the event timer is not configured to handle this situation, the event timer will disable itself. If we have enabled overflow, the counter will roll over and continue counting while generating a event-roll-over interrupt. We can use this capability to count longer events by counting the number of times the event rolls over before arriving at the final value.
While using one event timer allows us to measure the time a signal is high or low, we can use two event timers to measure both the high and low times for the same signal: one configured to measured the high time and another to measure the low time.
To use the TTC to monitor an event, we need to ensure the TTC is enabled on the MIO configuration tab of the Zynq customization dialog:
To measure an external signal, we need to configure the TTC to use an external signal. We do this on the Clock Congifuration tab of the Zynq customization dialog:
Enabling this external source on the Zynq processing system block diagram provides input ports that we can connect to the external signal we wish to monitor. In this case I have connected both event timer inputs to the same external signal to monitor the signal’s high and low durations.
When I implemented the design targeting an Avnet ZedBoard, I broke the wave outputs and clock inputs out to the board’s PMOD connector A.
To get the software up and running I used the Servo example that we generated earlier as a base. To use the event timers, we need to set the enable bit the Event Control Timer register. Within this register, we can enable the event timer, set the appropriate signal level, and enable overflow if desired.
The TTC files provided with the BSP do not provide functions to configure or use the event timers within the TTC. However, interacting with them is straightforward. We can use the Xil_Out16 and Xil_In16 functions to configure the event timer and to read the timer value.
To enable the TTC0 timers zero and one to count opposite events, we can use the commands shown below:
Once enabled, we can then read the TTC event timers. In the case of this example, we use the code snippet below:
event = Xil_In16(0xF8001078);
event = Xil_In16(0xF800107C);
These commands read the event timer value.
When I put this all together and stimulated the external input using a 5KHz signal with a range of duty cycles, I could correctly determine the signal’s high and low times.
For example, with a 70 % duty cycle the event timer recorded a time of 15556 for the high duration and time of 6667 for a low duration of the pulse. There are 22222 CPU_1x clock cycles in a 5KHz signal. The measurement captured in the event registers total 22224 CPU_1x clock cycles or a frequency of 4999.6 Hz with the correct duty cycles for the signal received.
To ensure the most accurate conversion of clock counts into actual time measurements, we can use the #define XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687 definition provided within xparameters.h. This is either 4 or 6 times the frequency of CPU_1x.
These event timers can prove very useful in our systems, especially if we are interfacing with sensors that provide PWM outputs such as some temperature and pressure sensors.
Code is available on Github as always.
If you want E book or hardback versions of previous MicroZed chronicle blogs, you can get them below.
Xilinx has just introduced a totally new technology for high-speed RF designs: an integrated RF-processing subsystem consisting of RF-class ADCs and DACs implemented on the same piece of 16nm UltraScale+ silicon along with the digital programmable-logic, microprocessor, and I/O circuits. This technology transforms the All Programmable Zynq UltraScale+ MPSoC into an RFSoC. The technology’s high-performance, direct-RF sampling simplifies the design of all sorts of RF systems while cutting power consumption, reducing the system’s form factor, and improving accuracy—driving every critical, system-level figure of merit in the right direction.
The fundamental converter technology behind this announcement was recently discussed in two ISSCC 2017 papers by Xilinx authors: “A 13b 4GS/s Digitally Assisted Dynamic 3-Stage Asynchronous Pipelined-SAR ADC” and “A 330mW 14b 6.8GS/s Dual-Mode RF DAC in 16nm FinFET Achieving -70.8dBc ACPR in a 20MHz Channel at 5.2GHz.” (You can download a PDF copy of those two papers here.)
This advanced RF converter technology vastly extends the company’s engineering developments that put high-speed, on-chip analog processing onto Xilinx All Programmable devices starting with the 1Msamples/sec XADC converters introduced on All Programmable 7 series devices way back in 2012. However, these new 16nm RFSoC converters are much, much faster—by more than three orders of magnitude. Per today’s technology announcement, the RFSoC’s integrated 12-bit ADC achieves 4Gsamples/sec and the integrated 14-bit DAC achieves 6.4Gsamples/sec, which places Xilinx RFSoC technology squarely into the arena for 5G direct-RF design as well as millimeter-wave backhaul, radar, and EW applications.
Here’s a block diagram of the RFSoC’s integrated RF subsystem:
Xilinx Zynq UltraScale+ RFSoC RF Subsystem
In addition to the analog converters, the RF Data Converter subsystem includes mixers, a numerically controlled oscillator (NCO), decimation/interpolation, and other DSP blocks dedicated to each channel. The RF subsystem can handle real and complex signals, required for IQ processing. The analog converters achieve high sample rates, large dynamic range, and the resolution required for 5G radio-head and backhaul applications. In some cases, the integrated digital down-conversion (DDC) built into the RF subsystem requires no additional FPGA resources.
The end result is breakthrough integration. The analog-to-digital signal chain, in particular, is supported by a hardened DSP subsystem for flexible configuration by the analog designer. This leads to a 50-75% reduction in system power and system footprint, along with the needed flexibility to adapt to evolving specifications and network topologies.
Where does that system-power reduction come from? The integration of both the digital and analog-conversion electronics on one piece of silicon eliminates a lot of power-hungry I/O and takes the analog converters down to the 16nm FinFET realm. Here’s a power-reduction table from the backgrounder with three MIMO radio example systems:
How about the form-factor reduction? Here’s a graphical example:
You save the pcb space needed by the converters and you save the space required to route all of the length-matched, serpentine pcb I/O traces between the converters and the digital SoCs. All of that I/O connectivity and the length matching now takes place on-chip.
To learn more about the All Programmable RFSoC architecture, click here or contact your friendly, neighborhood Xilinx sales representative.
Note: When we say “All Programmable” we mean it.